Bang-Sup Song, Myung-Jun Choe, P. Rakers, S. Gillig
{"title":"1 V 6 b 50 MHz电流插值CMOS ADC","authors":"Bang-Sup Song, Myung-Jun Choe, P. Rakers, S. Gillig","doi":"10.1109/VLSIC.1999.797242","DOIUrl":null,"url":null,"abstract":"A current-interpolation technique is used to implement a 6 b 50 MHz ADC operable with a single battery cell as low as 0.9 V without charge pumping. The prototype chip, fabricated in a 0.35 /spl mu/m standard digital process, occupies an area of 2.4 mm/spl times/2 mm, and consumes 10 mW each in analog and digital supplies, respectively.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"15 4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A 1 V 6 b 50 MHz current-interpolating CMOS ADC\",\"authors\":\"Bang-Sup Song, Myung-Jun Choe, P. Rakers, S. Gillig\",\"doi\":\"10.1109/VLSIC.1999.797242\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A current-interpolation technique is used to implement a 6 b 50 MHz ADC operable with a single battery cell as low as 0.9 V without charge pumping. The prototype chip, fabricated in a 0.35 /spl mu/m standard digital process, occupies an area of 2.4 mm/spl times/2 mm, and consumes 10 mW each in analog and digital supplies, respectively.\",\"PeriodicalId\":433264,\"journal\":{\"name\":\"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)\",\"volume\":\"15 4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-06-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1999.797242\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1999.797242","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A current-interpolation technique is used to implement a 6 b 50 MHz ADC operable with a single battery cell as low as 0.9 V without charge pumping. The prototype chip, fabricated in a 0.35 /spl mu/m standard digital process, occupies an area of 2.4 mm/spl times/2 mm, and consumes 10 mW each in analog and digital supplies, respectively.