1 V 6 b 50 MHz电流插值CMOS ADC

Bang-Sup Song, Myung-Jun Choe, P. Rakers, S. Gillig
{"title":"1 V 6 b 50 MHz电流插值CMOS ADC","authors":"Bang-Sup Song, Myung-Jun Choe, P. Rakers, S. Gillig","doi":"10.1109/VLSIC.1999.797242","DOIUrl":null,"url":null,"abstract":"A current-interpolation technique is used to implement a 6 b 50 MHz ADC operable with a single battery cell as low as 0.9 V without charge pumping. The prototype chip, fabricated in a 0.35 /spl mu/m standard digital process, occupies an area of 2.4 mm/spl times/2 mm, and consumes 10 mW each in analog and digital supplies, respectively.","PeriodicalId":433264,"journal":{"name":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","volume":"15 4 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A 1 V 6 b 50 MHz current-interpolating CMOS ADC\",\"authors\":\"Bang-Sup Song, Myung-Jun Choe, P. Rakers, S. Gillig\",\"doi\":\"10.1109/VLSIC.1999.797242\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A current-interpolation technique is used to implement a 6 b 50 MHz ADC operable with a single battery cell as low as 0.9 V without charge pumping. The prototype chip, fabricated in a 0.35 /spl mu/m standard digital process, occupies an area of 2.4 mm/spl times/2 mm, and consumes 10 mW each in analog and digital supplies, respectively.\",\"PeriodicalId\":433264,\"journal\":{\"name\":\"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)\",\"volume\":\"15 4 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-06-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1999.797242\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1999.797242","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7

摘要

采用电流插值技术实现了一个6 b 50 MHz的ADC,可在低至0.9 V的单个电池上工作,无需充电泵送。该原型芯片以0.35 /spl mu/m标准数字工艺制造,占地2.4 mm/spl × / 2mm,模拟电源和数字电源的功耗分别为10 mW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 1 V 6 b 50 MHz current-interpolating CMOS ADC
A current-interpolation technique is used to implement a 6 b 50 MHz ADC operable with a single battery cell as low as 0.9 V without charge pumping. The prototype chip, fabricated in a 0.35 /spl mu/m standard digital process, occupies an area of 2.4 mm/spl times/2 mm, and consumes 10 mW each in analog and digital supplies, respectively.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信