多波形5G通信的柔性基带调制器架构

M. Ferreira, J. Ferreira
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引用次数: 0

摘要

第五代(5G)革命不仅仅代表了前几代的性能增强:它将深刻改变人类和/或机器交互的方式,实现用例和服务数量的异构扩展。实现这一革命的关键是硬件组件的设计,其特点是高度的灵活性,多功能性和资源/功率效率。本章提出了一种面向现场可编程门阵列(FPGA)的基带处理架构,适用于4G/5G波形共存、不连续载波聚合(CA)或集中式云无线接入网(C-RAN)处理等快速变化的通信环境。该架构支持三种5G候选波形,具有可升级性、资源效率和成本效益。通过硬件虚拟化,通过动态部分重新配置(DPR),我们架构的设计空间探索超过了Zynq xc7z020设备上可用的硬件资源。此外,动态频率缩放(DFS)可以在运行时调整处理吞吐量,并将功耗降低高达88%。DPR和DFS的综合资源开销非常低,重构延迟比5G通信的控制平面延迟要求低两个数量级。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Flexible Baseband Modulator Architecture for Multi-Waveform 5G Communications
The fifth-generation (5G) revolution represents more than a mere performance enhancement of previous generations: it will deeply transform the way humans and/or machines interact, enabling a heterogeneous expansion in the number of use cases and services. Crucial to the realization of this revolution is the design of hardware components characterized by high degrees of flexibility, versatility and resource/power efficiency. This chapter proposes a field-programmable gate array (FPGA)-oriented baseband processing architecture suitable for fast-changing communication environments such as 4G/5G waveform coexistence, noncontiguous carrier aggregation (CA) or centralized cloud radio access network (C-RAN) processing. The proposed architecture supports three 5G waveform candidates and is shown to be upgradable, resource-efficient and cost-effective. Through hardware virtualization, enabled by dynamic partial reconfiguration (DPR), the design space exploration of our architecture exceeds the hardware resources available on the Zynq xc7z020 device. Moreover, dynamic frequency scaling (DFS) enables the runtime adjustment of processing throughput and power reductions by up to 88%. The combined resource overhead for DPR and DFS is very low, and the reconfiguration latency stays two orders of magnitude below the control plane latency requirements proposed for 5G communications.
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