{"title":"基于2q+1值深度神经网络的高通量检测电路","authors":"Naoto Soga, Ryosuke Kuramochi, Hiroki Nakahara","doi":"10.1109/ISMVL51352.2021.00032","DOIUrl":null,"url":null,"abstract":"The demands of applications using a high-speed deep learning models at data centers are rapidly increasing. However, most of these accelerators depend on many memory accesses and DSP blocks, which cause performance bottleneck. We present a lookup table (LUT) mapping to directly map convolutional layers, mainly used in modern deep learning models. To reduce the number of LUTs, we develop a training method for a sparse local convolution (SLC), which trains sparse convolutional layers with unshared weight kernels with 2q + 1-valued representation to eliminate a zero weight edge. Compared with conventional sparse CNN training methods, 88% of multiply-accumulate operations are reduced by SLC training while maintaining the same accuracy. We implement an LUT-based convolutional layer circuit with 105 to 106 LUTs, accommodated by data center FPGAs and operating at a high-speed at 500 MHz (500 MFPS).","PeriodicalId":129346,"journal":{"name":"2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A High-Throughput Detection Circuit based on 2q+1-Valued Deep Neural Networks\",\"authors\":\"Naoto Soga, Ryosuke Kuramochi, Hiroki Nakahara\",\"doi\":\"10.1109/ISMVL51352.2021.00032\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The demands of applications using a high-speed deep learning models at data centers are rapidly increasing. However, most of these accelerators depend on many memory accesses and DSP blocks, which cause performance bottleneck. We present a lookup table (LUT) mapping to directly map convolutional layers, mainly used in modern deep learning models. To reduce the number of LUTs, we develop a training method for a sparse local convolution (SLC), which trains sparse convolutional layers with unshared weight kernels with 2q + 1-valued representation to eliminate a zero weight edge. Compared with conventional sparse CNN training methods, 88% of multiply-accumulate operations are reduced by SLC training while maintaining the same accuracy. We implement an LUT-based convolutional layer circuit with 105 to 106 LUTs, accommodated by data center FPGAs and operating at a high-speed at 500 MHz (500 MFPS).\",\"PeriodicalId\":129346,\"journal\":{\"name\":\"2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISMVL51352.2021.00032\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE 51st International Symposium on Multiple-Valued Logic (ISMVL)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL51352.2021.00032","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A High-Throughput Detection Circuit based on 2q+1-Valued Deep Neural Networks
The demands of applications using a high-speed deep learning models at data centers are rapidly increasing. However, most of these accelerators depend on many memory accesses and DSP blocks, which cause performance bottleneck. We present a lookup table (LUT) mapping to directly map convolutional layers, mainly used in modern deep learning models. To reduce the number of LUTs, we develop a training method for a sparse local convolution (SLC), which trains sparse convolutional layers with unshared weight kernels with 2q + 1-valued representation to eliminate a zero weight edge. Compared with conventional sparse CNN training methods, 88% of multiply-accumulate operations are reduced by SLC training while maintaining the same accuracy. We implement an LUT-based convolutional layer circuit with 105 to 106 LUTs, accommodated by data center FPGAs and operating at a high-speed at 500 MHz (500 MFPS).