CMOS中2 MHz同步降压变换器的设计考虑

2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs Pub Date : 2004-05-24 DOI:10.1109/WCT.2004.239804

A. Fukui, J. Knight

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引用次数: 6

摘要

介绍了一种用于手机射频功率放大器的2mhz同步降压变换器的设计思想。特别强调的是与实现这种高开关频率与电流模式架构和廉价的0.5 /spl mu/m CMOS工艺相关的问题。

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Design considerations for a 2 MHz synchronous buck converter in CMOS

The design considerations for a 2 MHz synchronous buck converter for a cellular phone RF power amplifier supply are presented. Particular emphasis is placed on the problems associated with achieving this high switching frequency with a current-mode architecture and in an inexpensive 0.5 /spl mu/m CMOS process.

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2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs

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