S. Daud, R. B. Ahmad, Ong Bi Lynn, Zahereel Ishwar Abd Kareem, Latifah Munirah Kamarudin, P. Ehkan, M. N. M. Warip, R. R. Othman
{"title":"CPU负载和空闲状态对嵌入式处理器能耗的影响","authors":"S. Daud, R. B. Ahmad, Ong Bi Lynn, Zahereel Ishwar Abd Kareem, Latifah Munirah Kamarudin, P. Ehkan, M. N. M. Warip, R. R. Othman","doi":"10.1109/ICED.2014.7015766","DOIUrl":null,"url":null,"abstract":"Device power consumption is a serious design consideration especially for embedded systems. By reducing the power consumption of a particular system, we could effectively prolong the runtime of the system, allowing for longer operational condition of a particular system. Previous studies have suggested that the power characteristics of a modern embedded processor have since been improved with manufacturer's implementation of better energy-focused designs. Implementation of hardware optimization such as better clock and power gating have been shown to produce better energy usage during on-load and off-load processing. In this paper we benchmarked the energy use of a modern embedded processor and study the effects of idling time to the processor and system energy usage. We have found that the processor energy use is significantly reduced in the instant that the processor goes idle during the execution process. The idling time during a processing timeslice allows the processor to use significantly less energy without explicitly depending on a frequency scaling algorithm to reduce energy consumption. This power saving feature directly implemented inside the processor hardware have the possibility to render software based frequency scaling algorithm and DVFS method to be less effective in reducing energy usage.","PeriodicalId":143806,"journal":{"name":"2014 2nd International Conference on Electronic Design (ICED)","volume":"175 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"The effects of CPU load & idle state on embedded processor energy usage\",\"authors\":\"S. Daud, R. B. Ahmad, Ong Bi Lynn, Zahereel Ishwar Abd Kareem, Latifah Munirah Kamarudin, P. Ehkan, M. N. M. Warip, R. R. Othman\",\"doi\":\"10.1109/ICED.2014.7015766\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Device power consumption is a serious design consideration especially for embedded systems. By reducing the power consumption of a particular system, we could effectively prolong the runtime of the system, allowing for longer operational condition of a particular system. Previous studies have suggested that the power characteristics of a modern embedded processor have since been improved with manufacturer's implementation of better energy-focused designs. Implementation of hardware optimization such as better clock and power gating have been shown to produce better energy usage during on-load and off-load processing. In this paper we benchmarked the energy use of a modern embedded processor and study the effects of idling time to the processor and system energy usage. We have found that the processor energy use is significantly reduced in the instant that the processor goes idle during the execution process. The idling time during a processing timeslice allows the processor to use significantly less energy without explicitly depending on a frequency scaling algorithm to reduce energy consumption. This power saving feature directly implemented inside the processor hardware have the possibility to render software based frequency scaling algorithm and DVFS method to be less effective in reducing energy usage.\",\"PeriodicalId\":143806,\"journal\":{\"name\":\"2014 2nd International Conference on Electronic Design (ICED)\",\"volume\":\"175 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 2nd International Conference on Electronic Design (ICED)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICED.2014.7015766\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 2nd International Conference on Electronic Design (ICED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICED.2014.7015766","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The effects of CPU load & idle state on embedded processor energy usage
Device power consumption is a serious design consideration especially for embedded systems. By reducing the power consumption of a particular system, we could effectively prolong the runtime of the system, allowing for longer operational condition of a particular system. Previous studies have suggested that the power characteristics of a modern embedded processor have since been improved with manufacturer's implementation of better energy-focused designs. Implementation of hardware optimization such as better clock and power gating have been shown to produce better energy usage during on-load and off-load processing. In this paper we benchmarked the energy use of a modern embedded processor and study the effects of idling time to the processor and system energy usage. We have found that the processor energy use is significantly reduced in the instant that the processor goes idle during the execution process. The idling time during a processing timeslice allows the processor to use significantly less energy without explicitly depending on a frequency scaling algorithm to reduce energy consumption. This power saving feature directly implemented inside the processor hardware have the possibility to render software based frequency scaling algorithm and DVFS method to be less effective in reducing energy usage.