{"title":"一个30 ns (600 MOPS)的图像处理器，具有可重构的流水线结构","authors":"K. Aono, M. Toyokura, T. Araki","doi":"10.1109/CICC.1989.56825","DOIUrl":null,"url":null,"abstract":"A 30-ns (600-MOPS) image processor is described. The 200 K-transistor chip has been fabricated in a 1.2-μm CMOS. A reconfigurable pipeline architecture with an array of nine multiplier/accumulators (MAC) is implemented by interchanging its pipelined data paths. This allows it to perform both matrix products and convolutions, systolically, for the discrete cosine transform (DCT) and transversal filters at HDTV rate. 512 by 512-pixel image data can be computed in less than 7.9 ms with sufficient resolution","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":"{\"title\":\"A 30 ns (600 MOPS) image processor with a reconfigurable pipeline architecture\",\"authors\":\"K. Aono, M. Toyokura, T. Araki\",\"doi\":\"10.1109/CICC.1989.56825\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 30-ns (600-MOPS) image processor is described. The 200 K-transistor chip has been fabricated in a 1.2-μm CMOS. A reconfigurable pipeline architecture with an array of nine multiplier/accumulators (MAC) is implemented by interchanging its pipelined data paths. This allows it to perform both matrix products and convolutions, systolically, for the discrete cosine transform (DCT) and transversal filters at HDTV rate. 512 by 512-pixel image data can be computed in less than 7.9 ms with sufficient resolution\",\"PeriodicalId\":165054,\"journal\":{\"name\":\"1989 Proceedings of the IEEE Custom Integrated Circuits Conference\",\"volume\":\"16 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-05-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"13\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1989 Proceedings of the IEEE Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.1989.56825\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1989.56825","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 30 ns (600 MOPS) image processor with a reconfigurable pipeline architecture
A 30-ns (600-MOPS) image processor is described. The 200 K-transistor chip has been fabricated in a 1.2-μm CMOS. A reconfigurable pipeline architecture with an array of nine multiplier/accumulators (MAC) is implemented by interchanging its pipelined data paths. This allows it to perform both matrix products and convolutions, systolically, for the discrete cosine transform (DCT) and transversal filters at HDTV rate. 512 by 512-pixel image data can be computed in less than 7.9 ms with sufficient resolution
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