组合电路高层设计的形式化验证方法

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198) Pub Date : 1999-01-18 DOI:10.1109/ASPDAC.1999.760023

J. Kitamichi, Hiroyuki Kageyama, N. Funabiki

{"title":"组合电路高层设计的形式化验证方法","authors":"J. Kitamichi, Hiroyuki Kageyama, N. Funabiki","doi":"10.1109/ASPDAC.1999.760023","DOIUrl":null,"url":null,"abstract":"In this paper, we propose a formal verification method for combinatorial circuits at high level design. The specification is described by both integer and Boolean variables for input and output variables, and the implementation is described by only Boolean variables. Our verification method judges the equivalence between the specification and the implementation by deciding the truth of the Presburger sentence. We show experimental results on some benchmarks, such as a 4 bit ALU and multiplier, by our method.","PeriodicalId":201352,"journal":{"name":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-01-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Formal verification method for combinatorial circuits at high level design\",\"authors\":\"J. Kitamichi, Hiroyuki Kageyama, N. Funabiki\",\"doi\":\"10.1109/ASPDAC.1999.760023\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we propose a formal verification method for combinatorial circuits at high level design. The specification is described by both integer and Boolean variables for input and output variables, and the implementation is described by only Boolean variables. Our verification method judges the equivalence between the specification and the implementation by deciding the truth of the Presburger sentence. We show experimental results on some benchmarks, such as a 4 bit ALU and multiplier, by our method.\",\"PeriodicalId\":201352,\"journal\":{\"name\":\"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-01-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASPDAC.1999.760023\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASPDAC.1999.760023","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

本文提出了一种用于组合电路高层设计的形式化验证方法。规范由输入和输出变量的整数和布尔变量描述，而实现仅由布尔变量描述。我们的验证方法通过判定Presburger句子的真值来判断规范与实现之间的等价性。我们用我们的方法在一些基准测试上展示了实验结果，例如4位ALU和乘法器。

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Formal verification method for combinatorial circuits at high level design

In this paper, we propose a formal verification method for combinatorial circuits at high level design. The specification is described by both integer and Boolean variables for input and output variables, and the implementation is described by only Boolean variables. Our verification method judges the equivalence between the specification and the implementation by deciding the truth of the Presburger sentence. We show experimental results on some benchmarks, such as a 4 bit ALU and multiplier, by our method.

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Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)

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