A monolithic 0.77W/mm2 power dense capacitive DC-DC step-down converter in 90nm Bulk CMOS

A fully integrated capacitive DC-DC converter reporting an output power of 1.65W in a standard 90nm Bulk CMOS process is realized. This converter implements a 2:1 voltage step-down conversion from twice the nominal technology supply voltage. Peak power conversion efficiency was measured to be 69%. The chip measures 2.14mm2 including 12nF implemented in standard available MOS capacitors. These baseline MOS capacitors, along with the introduced Flying Well approach and the Intrinsic Charge Recycling approach, result in a maximum power density of 0.77W/mm2. The converter is controllable through an on-chip voltage controlled oscillator (VCO) generating the clock signals for each of the 21 interleaved converter cores of this multiphase implementation. The implemented core interleaving allows for an output voltage ripple smaller than 8% of Vo without any dedicated output smoothing capacitor, saving die area and thus boosting the power density.