一个用于部分可重构异构soc设计和编程的开源平台

2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) Pub Date : 2022-10-01 DOI:10.1109/CASES55004.2022.00019

Biruk B. Seyoum, Davide Giri, Kuan-Lin Chiu, L. Carloni

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引用次数: 0

摘要

动态部分重构(DPR)使灵活、可扩展和健壮的自适应系统的设计和实现成为可能。我们提出了一种基于FPGA的部分可重构异构soc的DPR流程，该流程使用增量编译技术来减少FPGA的总编译时间。

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Work-in-Progress: An Open-Source Platform for Design and Programming of Partially Reconfigurable Heterogeneous SoCs

Dynamic partial reconfiguration (DPR) enables the design and implementation of flexible, scalable and robust adaptive systems. We present an FPGA-based DPR flow for partially reconfigurable heterogeneous SoCs that uses an incremental compilation technique to reduce the total FPGA compilation time.

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来源期刊

2022 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)

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