{"title":"PCB堆叠对WLCSP温度循环可靠性的影响","authors":"R. Roucou, R. Rongen, J.J. M Zaal, P. van der Wel","doi":"10.1109/ESTC.2018.8547202","DOIUrl":null,"url":null,"abstract":"This paper describes the use of a failure mechanism driven approach to develop and assess the reliability of new products during qualification. Due to their construction, Wafer Level Chip Scale Packages (WLCSP) have an increased interaction with the Printed Circuit Board (PCB) compared to more traditional packages. While mounted on the PCB, the thermo-mechanical stress during temperature cycling induces stress to the component via the solder joint. This stress can lead to cracks in the passivation layer, which propagates into the back end of line layers below and thus lead to an electrical failure of the component. On the one hand, the definition of the PCB (i.e. material and design) should mimic the stress from the final application (e.g. smart phone) and therefore be close to the application board. On the other hand, it must fulfill the requirements of the reliability stress testing by enabling the electrical testing of the component and surviving a larger stress as compared to the application.This study focusses on the effect of the PCB material (FR-4, FR-5 and Polyimide), its thickness (from 0.5mm to 1.6mm) and the number of copper layers in the PCB (from 4 layers to 10 layers). For these PCB variations, 6 configurations are defined and the components are subjected to temperature cycling stress testing. Based on the electrical failures due to cracks in the passivation, the effect of the stress is compared based on the statistical analysis of the failures rates. The 1.6mm PCB stack-ups with both polyimide and FR-4 are shown to induce more stress than the thinner PCBs. Due to its lower Young’s modulus compared to other materials, the thick FR-5 test carrier induces an equivalent stress compared to thinner FR-4 ones. The thinnest stack (0.5mm) being the least stressful for the passivation layer and the back end of line.In addition to the stress tests, finite element models are developed for a WLCSP mounted on various PCB configurations. Then, the thermo-mechanical stress is simulated and a good agreement is found with the performance ranking established from the application level temperature cycling test results. The outcome of this study enables the development of reliable components and the comparison of the stress during component qualification with the stress from its final assembly in the application.","PeriodicalId":198238,"journal":{"name":"2018 7th Electronic System-Integration Technology Conference (ESTC)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Effect of PCB stack-up on Temperature Cycling Reliability of WLCSP\",\"authors\":\"R. Roucou, R. Rongen, J.J. M Zaal, P. van der Wel\",\"doi\":\"10.1109/ESTC.2018.8547202\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the use of a failure mechanism driven approach to develop and assess the reliability of new products during qualification. Due to their construction, Wafer Level Chip Scale Packages (WLCSP) have an increased interaction with the Printed Circuit Board (PCB) compared to more traditional packages. While mounted on the PCB, the thermo-mechanical stress during temperature cycling induces stress to the component via the solder joint. This stress can lead to cracks in the passivation layer, which propagates into the back end of line layers below and thus lead to an electrical failure of the component. On the one hand, the definition of the PCB (i.e. material and design) should mimic the stress from the final application (e.g. smart phone) and therefore be close to the application board. On the other hand, it must fulfill the requirements of the reliability stress testing by enabling the electrical testing of the component and surviving a larger stress as compared to the application.This study focusses on the effect of the PCB material (FR-4, FR-5 and Polyimide), its thickness (from 0.5mm to 1.6mm) and the number of copper layers in the PCB (from 4 layers to 10 layers). For these PCB variations, 6 configurations are defined and the components are subjected to temperature cycling stress testing. Based on the electrical failures due to cracks in the passivation, the effect of the stress is compared based on the statistical analysis of the failures rates. The 1.6mm PCB stack-ups with both polyimide and FR-4 are shown to induce more stress than the thinner PCBs. Due to its lower Young’s modulus compared to other materials, the thick FR-5 test carrier induces an equivalent stress compared to thinner FR-4 ones. The thinnest stack (0.5mm) being the least stressful for the passivation layer and the back end of line.In addition to the stress tests, finite element models are developed for a WLCSP mounted on various PCB configurations. Then, the thermo-mechanical stress is simulated and a good agreement is found with the performance ranking established from the application level temperature cycling test results. The outcome of this study enables the development of reliable components and the comparison of the stress during component qualification with the stress from its final assembly in the application.\",\"PeriodicalId\":198238,\"journal\":{\"name\":\"2018 7th Electronic System-Integration Technology Conference (ESTC)\",\"volume\":\"108 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 7th Electronic System-Integration Technology Conference (ESTC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESTC.2018.8547202\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 7th Electronic System-Integration Technology Conference (ESTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESTC.2018.8547202","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Effect of PCB stack-up on Temperature Cycling Reliability of WLCSP
This paper describes the use of a failure mechanism driven approach to develop and assess the reliability of new products during qualification. Due to their construction, Wafer Level Chip Scale Packages (WLCSP) have an increased interaction with the Printed Circuit Board (PCB) compared to more traditional packages. While mounted on the PCB, the thermo-mechanical stress during temperature cycling induces stress to the component via the solder joint. This stress can lead to cracks in the passivation layer, which propagates into the back end of line layers below and thus lead to an electrical failure of the component. On the one hand, the definition of the PCB (i.e. material and design) should mimic the stress from the final application (e.g. smart phone) and therefore be close to the application board. On the other hand, it must fulfill the requirements of the reliability stress testing by enabling the electrical testing of the component and surviving a larger stress as compared to the application.This study focusses on the effect of the PCB material (FR-4, FR-5 and Polyimide), its thickness (from 0.5mm to 1.6mm) and the number of copper layers in the PCB (from 4 layers to 10 layers). For these PCB variations, 6 configurations are defined and the components are subjected to temperature cycling stress testing. Based on the electrical failures due to cracks in the passivation, the effect of the stress is compared based on the statistical analysis of the failures rates. The 1.6mm PCB stack-ups with both polyimide and FR-4 are shown to induce more stress than the thinner PCBs. Due to its lower Young’s modulus compared to other materials, the thick FR-5 test carrier induces an equivalent stress compared to thinner FR-4 ones. The thinnest stack (0.5mm) being the least stressful for the passivation layer and the back end of line.In addition to the stress tests, finite element models are developed for a WLCSP mounted on various PCB configurations. Then, the thermo-mechanical stress is simulated and a good agreement is found with the performance ranking established from the application level temperature cycling test results. The outcome of this study enables the development of reliable components and the comparison of the stress during component qualification with the stress from its final assembly in the application.