高k介电介质SiC功率mosfet的栅极阻抗分析

2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI:10.1109/ISPSD57135.2023.10147725

S. Race, Piyush Kumar, P. Natzke, Ivana Kovacevic-Badstuebner, M. E. Bathen, U. Grossner, G. Romano, Y. Arango, Sami Bolat, S. Wirths, L. Knoll, A. Mihaila

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引用次数: 1

摘要

本文展示了如何使用硅基功率MOSFET的栅极阻抗表征来研究其介电-半导体接口质量，从而区分沟道和JFET的贡献。$Z_{\text{gg}}$表征是对具有SiO2和高k栅极电介质的SiC功率mosfet进行的。$Z_{\text{gg}}$在各自的SiC mosfet中确定了不同的电压和温度依赖性。较新的设计在近半导体界面陷阱方面有了改进。实验表征和TCAD装置仿真验证了上述结论。

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Gate Impedance Analysis of SiC power MOSFETs with SiO2 and High-k Dielectric

This paper shows how the gate impedance $Z_{\text{gg}}$ characterization of a SiC-power MOSFET can be used to investigate its dielectric-semiconductor interface quality distinguishing the channel and JFET contributions. The $Z_{\text{gg}}$ characterization is performed for SiC power MOSFETs with SiO2 and with high-k gate dielectrics. Different voltage- and temperature-dependencies of $Z_{\text{gg}}$ are identified in the respective SiC MOSFETs. The newer designs show an improvement with respect to the near semiconductor interface-traps. Experimental characterization and TCAD device simulations are carried out to support the conclusions.

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2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)

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