低功耗GPS接收机设计

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374) Pub Date : 1998-10-08 DOI:10.1109/SIPS.1998.715763

T. Meng

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引用次数: 17

摘要

本文介绍了一种基于CMOS技术的低功耗全球定位系统(GPS)接收机的设计。主GPS测距信号以1.575 GHz的频率广播，由伪噪声序列以1 MHz的芯片速率调制。这款低功耗GPS接收机的设计强调了电路技术和架构折衷，以最大限度地减少每个位置估计所需的能量。

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Low-power GPS receiver design

This paper describes the design of a low-power global positioning system (GPS) receiver implemented in CMOS technology. The primary GPS ranging signal is broadcast at a frequency of 1.575 GHz, modulated by a pseudo-noise sequence at a chip rate of 1 MHz. The design of this low-power GPS receiver emphasizes the circuit techniques and architectural trade-offs employed in minimizing the energy needed for each position estimate.

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来源期刊

1998 IEEE Workshop on Signal Processing Systems. SIPS 98. Design and Implementation (Cat. No.98TH8374)

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