一种基于SIMOX的高性能低温0.3 μ m CMOS

1992 Symposium on VLSI Technology Digest of Technical Papers Pub Date : 1992-06-02 DOI:10.1109/VLSIT.1992.200671

G. Shahidi, B. Davari, T. Bucelot, D. Zicherman, P. McFarland, A. Fink, S. Brodsky, K. Pettrilo, N. Mazzeo, R. Lombardi, M. Rodriguez, M. Polcari, T. Ning

{"title":"一种基于SIMOX的高性能低温0.3 μ m CMOS","authors":"G. Shahidi, B. Davari, T. Bucelot, D. Zicherman, P. McFarland, A. Fink, S. Brodsky, K. Pettrilo, N. Mazzeo, R. Lombardi, M. Rodriguez, M. Polcari, T. Ning","doi":"10.1109/VLSIT.1992.200671","DOIUrl":null,"url":null,"abstract":"It is shown that ultrathin SOI offers a device design advantage for operation of CMOS circuits at 77 K. The use of ultrathin SOI makes it possible to achieve low threshold at relatively high channel doping, which is necessary for reduction of short channel effects. Very-high-performance loaded NAND inverters (with delays of less than 100 ps at 2 V) were fabricated.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A high performance low temperature 0.3 mu m CMOS on SIMOX\",\"authors\":\"G. Shahidi, B. Davari, T. Bucelot, D. Zicherman, P. McFarland, A. Fink, S. Brodsky, K. Pettrilo, N. Mazzeo, R. Lombardi, M. Rodriguez, M. Polcari, T. Ning\",\"doi\":\"10.1109/VLSIT.1992.200671\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"It is shown that ultrathin SOI offers a device design advantage for operation of CMOS circuits at 77 K. The use of ultrathin SOI makes it possible to achieve low threshold at relatively high channel doping, which is necessary for reduction of short channel effects. Very-high-performance loaded NAND inverters (with delays of less than 100 ps at 2 V) were fabricated.<<ETX>>\",\"PeriodicalId\":404756,\"journal\":{\"name\":\"1992 Symposium on VLSI Technology Digest of Technical Papers\",\"volume\":\"22 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-06-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1992 Symposium on VLSI Technology Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1992.200671\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1992 Symposium on VLSI Technology Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1992.200671","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

结果表明，超薄SOI在77 K下的CMOS电路中具有器件设计优势。超薄SOI的使用使得在相对高的通道掺杂下实现低阈值成为可能，这是减少短通道效应所必需的。制作了高性能负载NAND逆变器(在2 V时延迟小于100 ps)。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A high performance low temperature 0.3 mu m CMOS on SIMOX

It is shown that ultrathin SOI offers a device design advantage for operation of CMOS circuits at 77 K. The use of ultrathin SOI makes it possible to achieve low threshold at relatively high channel doping, which is necessary for reduction of short channel effects. Very-high-performance loaded NAND inverters (with delays of less than 100 ps at 2 V) were fabricated.<>

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

1992 Symposium on VLSI Technology Digest of Technical Papers

自引率

0.00%

发文量