{"title":"一种低能耗自适应总线编码方案","authors":"B. Bishop, A. Bahuman","doi":"10.1109/IWV.2001.923149","DOIUrl":null,"url":null,"abstract":"We have extracted run-time memory access traces from the Mediabench benchmark set. These traces exhibit a high degree of repetition. We propose an adaptive bus coding scheme that will reduce transition activity by exploiting value repetition. For this scheme, we introduce an extra bitline similar to bus-invert coding.","PeriodicalId":114059,"journal":{"name":"Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"A low-energy adaptive bus coding scheme\",\"authors\":\"B. Bishop, A. Bahuman\",\"doi\":\"10.1109/IWV.2001.923149\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We have extracted run-time memory access traces from the Mediabench benchmark set. These traces exhibit a high degree of repetition. We propose an adaptive bus coding scheme that will reduce transition activity by exploiting value repetition. For this scheme, we introduce an extra bitline similar to bus-invert coding.\",\"PeriodicalId\":114059,\"journal\":{\"name\":\"Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems\",\"volume\":\"21 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-04-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWV.2001.923149\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWV.2001.923149","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
We have extracted run-time memory access traces from the Mediabench benchmark set. These traces exhibit a high degree of repetition. We propose an adaptive bus coding scheme that will reduce transition activity by exploiting value repetition. For this scheme, we introduce an extra bitline similar to bus-invert coding.