{"title":"高效的四路行拆分分层QC-LDPC解码器架构","authors":"T. Nguyen, Hanho Lee","doi":"10.1109/ISOCC.2018.8649976","DOIUrl":null,"url":null,"abstract":"This paper presents a four-way row-splitting architecture for layered low-density parity-check (LDPC) decoder. Based on the proposed method, an efficient partially parallel pipelined QC-LDPC decoder is proposed. The synthesis results using TSMC 40-nm standard cell CMOS technology show that the proposed decoder achieves the maximum required throughput of 7.05 Gb/s and outperforms its predecessors in terms of area efficiency.","PeriodicalId":127156,"journal":{"name":"2018 International SoC Design Conference (ISOCC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Efficient Four-way Row-splitting Layered QC-LDPC Decoder Architecture\",\"authors\":\"T. Nguyen, Hanho Lee\",\"doi\":\"10.1109/ISOCC.2018.8649976\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a four-way row-splitting architecture for layered low-density parity-check (LDPC) decoder. Based on the proposed method, an efficient partially parallel pipelined QC-LDPC decoder is proposed. The synthesis results using TSMC 40-nm standard cell CMOS technology show that the proposed decoder achieves the maximum required throughput of 7.05 Gb/s and outperforms its predecessors in terms of area efficiency.\",\"PeriodicalId\":127156,\"journal\":{\"name\":\"2018 International SoC Design Conference (ISOCC)\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC.2018.8649976\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC.2018.8649976","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents a four-way row-splitting architecture for layered low-density parity-check (LDPC) decoder. Based on the proposed method, an efficient partially parallel pipelined QC-LDPC decoder is proposed. The synthesis results using TSMC 40-nm standard cell CMOS technology show that the proposed decoder achieves the maximum required throughput of 7.05 Gb/s and outperforms its predecessors in terms of area efficiency.
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