Hyeokjoon Yang, Hyunbae Lee, Hanseul Kim, Sangwook Park, J. Burm
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引用次数: 0
摘要
本文提出了一种采用RC两步法的2MS/$s$ 12位SAR ADC。SAR ADC需要在尺寸和高分辨率规格之间进行权衡。随着ADC分辨率的提高，电容阵列的总电容呈指数级增长，因此电容阵列存在尺寸问题。为了克服这一问题，本文提出的SAR ADC采用电阻阵列和电容阵列。此外，所提出的SAR ADC对每个比特采用不同的比特循环时间。采用28纳米CMOS技术实现了原型ADC。在1.0 v电源下，芯片功耗为221µW。ADC核心的有效面积为0.02mm x 0.79mm。
A 12-b 2 MS/s R-C Two-Step SAR ADC with Bit-Cycling Time Control and LSB Correction Logic
This paper presents a 2MS/$s$ 12-bit SAR ADC with RC two-step scheme. The SAR ADC has trade-off between size and high-resolution specification. The capacitor array has size problem because total capacitance of capacitor array increases exponentially as the ADC resolution increase. To overcome this issue, the proposed SAR ADC is used the resistor array with the capacitor array. Also, the proposed SAR ADC applied different bit-cycling time for each bit. A prototype ADC was implemented in a 28-nm CMOS technology. The chip consumes 221µW under a 1.0-V supply. The ADC core occupies an active area of 0.02mm x 0.79mm.
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