A. Benso, S. Chiusano, G. D. Natale, P. Prinetto, Monica Lobetti Bodoni
{"title":"一种自我修复的SRAM内核系列","authors":"A. Benso, S. Chiusano, G. D. Natale, P. Prinetto, Monica Lobetti Bodoni","doi":"10.1109/OLT.2000.856639","DOIUrl":null,"url":null,"abstract":"In the present paper a family of BISR SRAM cores is proposed, characterized by a self-repair strategy performed on-line and without user intervention. Moreover, w.r.t. the BISR approaches presented so far, the proposed method is independent from the memory physical layout. In addition to the BISR architecture, to detect the faulty cells to be repaired, a complete set of test solutions is proposed ranging from an external test to an on-line concurrent BIST.","PeriodicalId":334770,"journal":{"name":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"27","resultStr":"{\"title\":\"A family of self-repair SRAM cores\",\"authors\":\"A. Benso, S. Chiusano, G. D. Natale, P. Prinetto, Monica Lobetti Bodoni\",\"doi\":\"10.1109/OLT.2000.856639\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In the present paper a family of BISR SRAM cores is proposed, characterized by a self-repair strategy performed on-line and without user intervention. Moreover, w.r.t. the BISR approaches presented so far, the proposed method is independent from the memory physical layout. In addition to the BISR architecture, to detect the faulty cells to be repaired, a complete set of test solutions is proposed ranging from an external test to an on-line concurrent BIST.\",\"PeriodicalId\":334770,\"journal\":{\"name\":\"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-07-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"27\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/OLT.2000.856639\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/OLT.2000.856639","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In the present paper a family of BISR SRAM cores is proposed, characterized by a self-repair strategy performed on-line and without user intervention. Moreover, w.r.t. the BISR approaches presented so far, the proposed method is independent from the memory physical layout. In addition to the BISR architecture, to detect the faulty cells to be repaired, a complete set of test solutions is proposed ranging from an external test to an on-line concurrent BIST.
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