H. Kim, Sang-Bo Lee, D. Choi, J. Shim, Kyu-Han Lee, Kyupil Lee, Kinam Kim, Jong-Woo Park
{"title":"基于薄膜SOI的高性能16M DRAM","authors":"H. Kim, Sang-Bo Lee, D. Choi, J. Shim, Kyu-Han Lee, Kyupil Lee, Kinam Kim, Jong-Woo Park","doi":"10.1109/VLSIT.1995.520898","DOIUrl":null,"url":null,"abstract":"A fully working 16M DRAM on a Thin Film Silicon On Insulator (TFSOI) is made with 0.5 /spl mu/m CMOS technology. This is, to the best of our knowledge, the highest density SOI DRAM ever achieved. LOCOS isolation and Local Implantation post Field oxidation (LIF) are introduced to suppress the edge transistor effect in NMOS. A reduced n/sup +//p/sup +/ dose in S/D implantation is the key process for a high density TFSOI-DRAM to suppress the defect generation during process while drain-source breakdown voltage (BVds) being increased. The shmoo plot of supply voltage vs. TRAC at 25/spl deg/C for a TFSOI-DRAM is demonstrated. RAS access time, TRAC, is 50 ns at 3.0 V Vcc which is faster by 20% than that of the equivalent bulk-Si device.","PeriodicalId":328379,"journal":{"name":"1995 Symposium on VLSI Technology. Digest of Technical Papers","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"20","resultStr":"{\"title\":\"A high performance 16M DRAM on a thin film SOI\",\"authors\":\"H. Kim, Sang-Bo Lee, D. Choi, J. Shim, Kyu-Han Lee, Kyupil Lee, Kinam Kim, Jong-Woo Park\",\"doi\":\"10.1109/VLSIT.1995.520898\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fully working 16M DRAM on a Thin Film Silicon On Insulator (TFSOI) is made with 0.5 /spl mu/m CMOS technology. This is, to the best of our knowledge, the highest density SOI DRAM ever achieved. LOCOS isolation and Local Implantation post Field oxidation (LIF) are introduced to suppress the edge transistor effect in NMOS. A reduced n/sup +//p/sup +/ dose in S/D implantation is the key process for a high density TFSOI-DRAM to suppress the defect generation during process while drain-source breakdown voltage (BVds) being increased. The shmoo plot of supply voltage vs. TRAC at 25/spl deg/C for a TFSOI-DRAM is demonstrated. RAS access time, TRAC, is 50 ns at 3.0 V Vcc which is faster by 20% than that of the equivalent bulk-Si device.\",\"PeriodicalId\":328379,\"journal\":{\"name\":\"1995 Symposium on VLSI Technology. Digest of Technical Papers\",\"volume\":\"21 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-06-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"20\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1995 Symposium on VLSI Technology. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1995.520898\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1995 Symposium on VLSI Technology. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1995.520898","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 20
摘要
采用0.5 /spl μ l /m CMOS技术，在薄膜绝缘体(TFSOI)上制造出完全工作的16M DRAM。据我们所知，这是有史以来密度最高的SOI DRAM。引入LOCOS隔离和局部注入后场氧化(LIF)来抑制NMOS中的边缘晶体管效应。降低S/D注入过程中的n/sup +//p/sup +/剂量是抑制高密度TFSOI-DRAM在漏源击穿电压(BVds)升高的过程中缺陷产生的关键工艺。给出了TFSOI-DRAM在25/spl度/C时电源电压与TRAC的平滑图。在3.0 V Vcc下，RAS的访问时间TRAC为50 ns，比等效的大块硅器件快20%。
A fully working 16M DRAM on a Thin Film Silicon On Insulator (TFSOI) is made with 0.5 /spl mu/m CMOS technology. This is, to the best of our knowledge, the highest density SOI DRAM ever achieved. LOCOS isolation and Local Implantation post Field oxidation (LIF) are introduced to suppress the edge transistor effect in NMOS. A reduced n/sup +//p/sup +/ dose in S/D implantation is the key process for a high density TFSOI-DRAM to suppress the defect generation during process while drain-source breakdown voltage (BVds) being increased. The shmoo plot of supply voltage vs. TRAC at 25/spl deg/C for a TFSOI-DRAM is demonstrated. RAS access time, TRAC, is 50 ns at 3.0 V Vcc which is faster by 20% than that of the equivalent bulk-Si device.
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