Si栅极全能(GAA)纳米线中ESD器件的vfTLP特性

2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD) Pub Date : 1900-01-01 DOI:10.1109/EOSESD.2016.7592555

Shih-Hung Chen, D. Linten, G. Hellings, A. Veloso, M. Scholz, R. Boschke, G. Groeseneken, N. Collaert, N. Horiguchi, A. Thean

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引用次数: 0

摘要

在7nm节点之外，栅极全能(GAA)纳米线(NW)是一种很有前途的器件结构。然而，新的架构可能导致内在的ESD性能下降。在本工作中，我们研究了GAA ESD器件的vfTLP特性。瞬态分析使我们对GAA器件在CDM ESD事件中的物理失效机制有了深入的了解。

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vfTLP characteristics of ESD devices in Si gate-all-around (GAA) nanowires

Beyond 7nm nodes, gate-all-around (GAA) nanowire (NW) is a promising device architecture. However, new architecture can result in intrinsic ESD performance degradation. In this work, we study vfTLP characteristics of GAA ESD devices. Transient analysis bring an in-depth understanding on physical failure mechanism of GAA devices during CDM ESD events.

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2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)

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