常规处理器阵列的能量/功率估计

15th International Symposium on System Synthesis, 2002. Pub Date : 2002-10-02 DOI:10.1145/581199.581212

S. Rajopadhye, Steven Derrien

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引用次数: 4

摘要

我们提出了一个高级分析模型，用于估计环路程序的VLSI处理器(收缩)阵列实现中的能量和/或功耗，特别是基于FPGA的协处理器的实现。我们专注于阵列设计参数对整体片外I/O流量以及阵列中本地存储器的数量和大小的各自影响。该模型经实验验证，结果良好(预测均方根误差为12.7%)。

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Energy/power estimation of regular processor arrays

We propose a high-level analytical model for estimating the energy and/or power dissipation in VLSI processor (systolic) array implementations of loop programs, particularly for implementations on FPGA based CO-processors. We focus on the respective impact of the array design parameters on the overall off-chip I/O traffic and the number and sizes of the local memories in the array. The model is validated experimentally and shows good results (12.7% RMS error in the predictions).

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来源期刊

15th International Symposium on System Synthesis, 2002.

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