一种准静态算术编码器的结构

Sabin Belu, D. Coltuc
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引用次数: 0

摘要

本文提出了一种新的算法编码器结构——准静态编码器。与经典实现不同,准静态编码器缓冲输入流,并使用静态模型对缓冲区中的数据进行编码。这种方法的最大优点是获得了更高的编码速度,但代价是压缩率略有下降。准静态编码器在英文文本、日志文件和二进制文件三种类型的数据上进行了测试,并与两种动态算法编码器进行了比较。对于128kB缓冲区,准静态编码器比动态编码器快3.6倍。压缩率的损失取决于数据类型和所考虑的动态实现。准静态编码器在英文文本和exe文件上优于Dippenstein的实现,并且低于Sachin Garg的实现,后者的压缩率在0.08到0.20 bpb之间。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
The Anatomy of a Quasi-Static Arithmetic Encoder
The paper proposes a new architecture for arithmetic encoders called Quasi-Static. Unlike the classical implementations, the Quasi-Static Encoder buffers the input stream and uses a static model for encoding the data in the buffer. The big advantage of such approach is the higher encoding speed obtained however with the price of slight degraded compression rates. The Quasi-Static Encoder is tested on three types of data - English text, log files and binary files - and compared with two dynamic arithmetic encoders. For 128kB buffers, the Quasi-Static Encoder is about 3.6 times faster than the dynamic counterparts. The loss in compression rate depends on data type and the considered dynamic implementation. The Quasi-Static Encoder outperforms Dippenstein's implementation on English texts and exe files and is below Sachin Garg implementation that gains between 0.08 and 0.20 bpb in compression rate.
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