V. Stachetti, J. Gaisler, G. Goller, C. Le Gargasson
{"title":"嵌入式空间飞行应用的32位处理单元","authors":"V. Stachetti, J. Gaisler, G. Goller, C. Le Gargasson","doi":"10.1109/RADECS.1995.509779","DOIUrl":null,"url":null,"abstract":"This paper describes the concurrent error-detection methods as well as the design and layout hardening techniques employed in the ERC 32, a 32-bit modular fault-tolerant processing core for embedded space flight applications. The core consists of three devices: an Integer Unit (IU), a Floating Point Unit (FPU), and a Memory Controller (MEC).","PeriodicalId":310087,"journal":{"name":"Proceedings of the Third European Conference on Radiation and its Effects on Components and Systems","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"32-bit processing unit for embedded space flight applications\",\"authors\":\"V. Stachetti, J. Gaisler, G. Goller, C. Le Gargasson\",\"doi\":\"10.1109/RADECS.1995.509779\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the concurrent error-detection methods as well as the design and layout hardening techniques employed in the ERC 32, a 32-bit modular fault-tolerant processing core for embedded space flight applications. The core consists of three devices: an Integer Unit (IU), a Floating Point Unit (FPU), and a Memory Controller (MEC).\",\"PeriodicalId\":310087,\"journal\":{\"name\":\"Proceedings of the Third European Conference on Radiation and its Effects on Components and Systems\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-09-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the Third European Conference on Radiation and its Effects on Components and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RADECS.1995.509779\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the Third European Conference on Radiation and its Effects on Components and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RADECS.1995.509779","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
摘要
本文介绍了用于嵌入式航天应用的32位模块化容错处理核心erc32中采用的并发错误检测方法以及设计和布局强化技术。核心由三个器件组成:IU (Integer Unit)、FPU (Floating Point Unit)和MEC (Memory Controller)。
32-bit processing unit for embedded space flight applications
This paper describes the concurrent error-detection methods as well as the design and layout hardening techniques employed in the ERC 32, a 32-bit modular fault-tolerant processing core for embedded space flight applications. The core consists of three devices: an Integer Unit (IU), a Floating Point Unit (FPU), and a Memory Controller (MEC).