{"title":"速度优化LUT基于' K '维度可重复使用的VQ编码器核心","authors":"K. Rasane, Dr. R. Srinivasa Rao Kunte","doi":"10.1109/ICECTECH.2010.5479963","DOIUrl":null,"url":null,"abstract":"This paper presents a review and improvement in the architecture of our earlier work presenting the ‘k Dimensional 4 codebook encoder’. A new VLSI LUT based “Mean Square distortion error” core is introduced in the VQ Encoder architecture. The paper focuses mainly on the modified technique utilized in our new VQ Encoder architecture which utilizes the repeatability and symmetric property observed in the Mean Square error calculations thereby completely eliminating the multiplication or addition data processing required for the MSE(Mean Square distortion error). This has resulted in improving the processing speed and has incorporated simplicity in the design by introducing an LUT, instead of the exhaustive arithmetic processing. This improved MSE module has been designed, implemented and tested in VHDL and synthesized and simulated. The improved hardware design can be used to easily build a larger VQ system by incorporating multiple such reusable cores. This makes the complete system design more modular with predictable delay and hence more suitable for time multiplexed wireless applications in real time Image Compression applications with processing speed of greater than 30 frames/sec.","PeriodicalId":178300,"journal":{"name":"2010 2nd International Conference on Electronic Computer Technology","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Speed optimized LUT based ‘K’ Dimensional reusable VQ Encoder core\",\"authors\":\"K. Rasane, Dr. R. Srinivasa Rao Kunte\",\"doi\":\"10.1109/ICECTECH.2010.5479963\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a review and improvement in the architecture of our earlier work presenting the ‘k Dimensional 4 codebook encoder’. A new VLSI LUT based “Mean Square distortion error” core is introduced in the VQ Encoder architecture. The paper focuses mainly on the modified technique utilized in our new VQ Encoder architecture which utilizes the repeatability and symmetric property observed in the Mean Square error calculations thereby completely eliminating the multiplication or addition data processing required for the MSE(Mean Square distortion error). This has resulted in improving the processing speed and has incorporated simplicity in the design by introducing an LUT, instead of the exhaustive arithmetic processing. This improved MSE module has been designed, implemented and tested in VHDL and synthesized and simulated. The improved hardware design can be used to easily build a larger VQ system by incorporating multiple such reusable cores. This makes the complete system design more modular with predictable delay and hence more suitable for time multiplexed wireless applications in real time Image Compression applications with processing speed of greater than 30 frames/sec.\",\"PeriodicalId\":178300,\"journal\":{\"name\":\"2010 2nd International Conference on Electronic Computer Technology\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-05-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 2nd International Conference on Electronic Computer Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECTECH.2010.5479963\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 2nd International Conference on Electronic Computer Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECTECH.2010.5479963","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Speed optimized LUT based ‘K’ Dimensional reusable VQ Encoder core
This paper presents a review and improvement in the architecture of our earlier work presenting the ‘k Dimensional 4 codebook encoder’. A new VLSI LUT based “Mean Square distortion error” core is introduced in the VQ Encoder architecture. The paper focuses mainly on the modified technique utilized in our new VQ Encoder architecture which utilizes the repeatability and symmetric property observed in the Mean Square error calculations thereby completely eliminating the multiplication or addition data processing required for the MSE(Mean Square distortion error). This has resulted in improving the processing speed and has incorporated simplicity in the design by introducing an LUT, instead of the exhaustive arithmetic processing. This improved MSE module has been designed, implemented and tested in VHDL and synthesized and simulated. The improved hardware design can be used to easily build a larger VQ system by incorporating multiple such reusable cores. This makes the complete system design more modular with predictable delay and hence more suitable for time multiplexed wireless applications in real time Image Compression applications with processing speed of greater than 30 frames/sec.