Sun Chao, Qi Hui, Su Tong, Ma Junzhi, Zhu Yongjie, Ding Jianjun
{"title":"基于FPGA的FIR滤波器设计","authors":"Sun Chao, Qi Hui, Su Tong, Ma Junzhi, Zhu Yongjie, Ding Jianjun","doi":"10.1109/ITNEC48623.2020.9084880","DOIUrl":null,"url":null,"abstract":"The filter designed by the analog circuit has a big problem. It is extremely convenient to design the FIR filter in the FPGA. In the article we will introduce the whole process of the entire FIR filter from design, verification, simulation to implementation. This paper mainly explains the FIR filter principle and filter coefficient calculation, and simulates the linear filter with the sampling rate of 1Mhz, the passband is 120Khz, and the order is 15th order. Finally, the experimental verification is carried out through the FPGA board, and the corresponding The design of the required FIR filter.","PeriodicalId":235524,"journal":{"name":"2020 IEEE 4th Information Technology, Networking, Electronic and Automation Control Conference (ITNEC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of FIR filter based on FPGA\",\"authors\":\"Sun Chao, Qi Hui, Su Tong, Ma Junzhi, Zhu Yongjie, Ding Jianjun\",\"doi\":\"10.1109/ITNEC48623.2020.9084880\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The filter designed by the analog circuit has a big problem. It is extremely convenient to design the FIR filter in the FPGA. In the article we will introduce the whole process of the entire FIR filter from design, verification, simulation to implementation. This paper mainly explains the FIR filter principle and filter coefficient calculation, and simulates the linear filter with the sampling rate of 1Mhz, the passband is 120Khz, and the order is 15th order. Finally, the experimental verification is carried out through the FPGA board, and the corresponding The design of the required FIR filter.\",\"PeriodicalId\":235524,\"journal\":{\"name\":\"2020 IEEE 4th Information Technology, Networking, Electronic and Automation Control Conference (ITNEC)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE 4th Information Technology, Networking, Electronic and Automation Control Conference (ITNEC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ITNEC48623.2020.9084880\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE 4th Information Technology, Networking, Electronic and Automation Control Conference (ITNEC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ITNEC48623.2020.9084880","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The filter designed by the analog circuit has a big problem. It is extremely convenient to design the FIR filter in the FPGA. In the article we will introduce the whole process of the entire FIR filter from design, verification, simulation to implementation. This paper mainly explains the FIR filter principle and filter coefficient calculation, and simulates the linear filter with the sampling rate of 1Mhz, the passband is 120Khz, and the order is 15th order. Finally, the experimental verification is carried out through the FPGA board, and the corresponding The design of the required FIR filter.