H. Yanagita, Akihito Jingu, S. Okanishi, S. Tanaka, T. Koyama
{"title":"实现“骨架晶圆”测试,用于电气故障分析","authors":"H. Yanagita, Akihito Jingu, S. Okanishi, S. Tanaka, T. Koyama","doi":"10.1109/ISSM.2018.8651160","DOIUrl":null,"url":null,"abstract":"This paper proposes a highly cost-efficient failure analysis method for yield enhancement. A fully automatic “skeleton wafer” testing system has been developed. This system has performed high-throughput accurate probing on each bare die on a sawn wafer from which many chips have been taken away and has enabled high success rate of diagnosis. Extended application for high-temperature measurement was also demonstrated.","PeriodicalId":262428,"journal":{"name":"2018 International Symposium on Semiconductor Manufacturing (ISSM)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Realization of “skeleton wafer” testing for electrical failure analysis\",\"authors\":\"H. Yanagita, Akihito Jingu, S. Okanishi, S. Tanaka, T. Koyama\",\"doi\":\"10.1109/ISSM.2018.8651160\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a highly cost-efficient failure analysis method for yield enhancement. A fully automatic “skeleton wafer” testing system has been developed. This system has performed high-throughput accurate probing on each bare die on a sawn wafer from which many chips have been taken away and has enabled high success rate of diagnosis. Extended application for high-temperature measurement was also demonstrated.\",\"PeriodicalId\":262428,\"journal\":{\"name\":\"2018 International Symposium on Semiconductor Manufacturing (ISSM)\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 International Symposium on Semiconductor Manufacturing (ISSM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSM.2018.8651160\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 International Symposium on Semiconductor Manufacturing (ISSM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSM.2018.8651160","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Realization of “skeleton wafer” testing for electrical failure analysis
This paper proposes a highly cost-efficient failure analysis method for yield enhancement. A fully automatic “skeleton wafer” testing system has been developed. This system has performed high-throughput accurate probing on each bare die on a sawn wafer from which many chips have been taken away and has enabled high success rate of diagnosis. Extended application for high-temperature measurement was also demonstrated.