{"title":"利用编译器进行数字GaAs集成电路的设计","authors":"R. Oettel","doi":"10.1109/GAAS.1993.394499","DOIUrl":null,"url":null,"abstract":"The ultimate performance of an integrated circuit can be substantially improved by using a compiler-based tool for its design. This is particularly true for gallium arsenide circuits where speed performance is critical, the cost of real estate is high, and design expertise is scarce. Furthermore, now that high levels of integration are possible with GaAs, automated layout tools are needed to manage the complexity and simultaneously preserve the performance potential of the technology. The result of applying compiler methodology to several generations of gallium arsenide technology over an eight year period is reported.<<ETX>>","PeriodicalId":347339,"journal":{"name":"15th Annual GaAs IC Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"The use of compilers for digital GaAs IC design\",\"authors\":\"R. Oettel\",\"doi\":\"10.1109/GAAS.1993.394499\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The ultimate performance of an integrated circuit can be substantially improved by using a compiler-based tool for its design. This is particularly true for gallium arsenide circuits where speed performance is critical, the cost of real estate is high, and design expertise is scarce. Furthermore, now that high levels of integration are possible with GaAs, automated layout tools are needed to manage the complexity and simultaneously preserve the performance potential of the technology. The result of applying compiler methodology to several generations of gallium arsenide technology over an eight year period is reported.<<ETX>>\",\"PeriodicalId\":347339,\"journal\":{\"name\":\"15th Annual GaAs IC Symposium\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-10-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"15th Annual GaAs IC Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GAAS.1993.394499\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"15th Annual GaAs IC Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GAAS.1993.394499","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The ultimate performance of an integrated circuit can be substantially improved by using a compiler-based tool for its design. This is particularly true for gallium arsenide circuits where speed performance is critical, the cost of real estate is high, and design expertise is scarce. Furthermore, now that high levels of integration are possible with GaAs, automated layout tools are needed to manage the complexity and simultaneously preserve the performance potential of the technology. The result of applying compiler methodology to several generations of gallium arsenide technology over an eight year period is reported.<>
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