当遇到通过错配时,渐进式传输线匹配

M. Daraban, D. Pitica
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引用次数: 2

摘要

当涉及到传输线时,信号完整性(SI)问题的常见原因是在路由过程中引起的不匹配。在所有可能导致不匹配的原因中,过孔是最常见的。在文献中,提出了不同的方法来解决由过孔引起的SI问题:拼接过孔,将驱动器输出阻抗匹配到传输线的新值[1]。当印刷电路板(pcb)使用超过四层时,可以使用拼接过孔。此外,较小的串联匹配电阻值可以改善信号上升/下降时间,但也会增加振铃效应的幅度。本文提出了一种可以在四层PCB上使用的接收机信号改善方案。该方案在不增加振铃效应幅度的情况下,保持了驱动器输出与传输线修正阻抗匹配所获得的改进。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Progressive transmission line matching when encountering via mismatching
When it comes to transmission lines the common causes for signal integrity (SI) problems are the mismatches caused during the routing process. From all the possible causes for mismatches, vias are the most common ones. In the literature, different approaches are proposed to resolve the SI problems caused by vias: stitching vias, matching the driver output impedance to the transmission line's new value [1]. Stitching vias can be used when printed circuit boards (PCBs) are used with more than four layers. Additionally a smaller value for the series-matching resistor improves the signal rise/fall time, but also increases the ringing effect's amplitude. In the paper, a solution for improving the signal at the receiver is proposed that can be used even on four layer PCB. The proposed solution keeps the improvements obtained through matching the driver output to the transmission line's modified impedance, without increasing the ringing effect amplitude.
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