{"title":"一种咀嚼式串行信号处理元件的指令集设计","authors":"R. Cottrell","doi":"10.1109/ESSCIRC.1988.5468454","DOIUrl":null,"url":null,"abstract":"Programmable nibble-serial processors are an efficient means of implementation for signal processing algorithms involving the solution of difference equations. The architecture is based on a simple processing element, known as a Signal Processing Element (SPE), of which many could be fabricated on a single VLSI chip. This paper discusses the design of an instruction set for such an SPE, considering in particular the effects of data memory size, and the use of special purpose registers.","PeriodicalId":197244,"journal":{"name":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Instruction Set Design for a Nibble-Serial Signal Processing Element\",\"authors\":\"R. Cottrell\",\"doi\":\"10.1109/ESSCIRC.1988.5468454\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Programmable nibble-serial processors are an efficient means of implementation for signal processing algorithms involving the solution of difference equations. The architecture is based on a simple processing element, known as a Signal Processing Element (SPE), of which many could be fabricated on a single VLSI chip. This paper discusses the design of an instruction set for such an SPE, considering in particular the effects of data memory size, and the use of special purpose registers.\",\"PeriodicalId\":197244,\"journal\":{\"name\":\"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.1988.5468454\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC '88: Fourteenth European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.1988.5468454","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Instruction Set Design for a Nibble-Serial Signal Processing Element
Programmable nibble-serial processors are an efficient means of implementation for signal processing algorithms involving the solution of difference equations. The architecture is based on a simple processing element, known as a Signal Processing Element (SPE), of which many could be fabricated on a single VLSI chip. This paper discusses the design of an instruction set for such an SPE, considering in particular the effects of data memory size, and the use of special purpose registers.
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