{"title":"6.25 Gb/s决策反馈均衡器用于高速背板通信","authors":"Ming-zhu Zhou, En Zhu, Shoujun Wang, Zhigong Wang","doi":"10.1109/ICMMT.2007.381426","DOIUrl":null,"url":null,"abstract":"A 6.25 Gb/s two-tap DFE (decision feedback equalizer) in high-speed backplane receiver has been designed in a 0.18-mum CMOS. The pipelined architecture in the half-rate DFE achieves an increase in the transmitted data rate over conventional DFE with a small increase in area. Near end data is a 6.25 Gb/s PRBS10 with 0.5 Vp-p, and the DFE recovered data has been measured with jitter (pp) of 3 ps and a horizontal eye-opening of 0.97 UI, a vertical eye opening of 0.48 V.","PeriodicalId":409971,"journal":{"name":"2007 International Conference on Microwave and Millimeter Wave Technology","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2007-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 6.25 Gb/s Decision Feedback Equalizer used in SerDes for High-speed Backplane Communications\",\"authors\":\"Ming-zhu Zhou, En Zhu, Shoujun Wang, Zhigong Wang\",\"doi\":\"10.1109/ICMMT.2007.381426\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 6.25 Gb/s two-tap DFE (decision feedback equalizer) in high-speed backplane receiver has been designed in a 0.18-mum CMOS. The pipelined architecture in the half-rate DFE achieves an increase in the transmitted data rate over conventional DFE with a small increase in area. Near end data is a 6.25 Gb/s PRBS10 with 0.5 Vp-p, and the DFE recovered data has been measured with jitter (pp) of 3 ps and a horizontal eye-opening of 0.97 UI, a vertical eye opening of 0.48 V.\",\"PeriodicalId\":409971,\"journal\":{\"name\":\"2007 International Conference on Microwave and Millimeter Wave Technology\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-04-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 International Conference on Microwave and Millimeter Wave Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICMMT.2007.381426\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 International Conference on Microwave and Millimeter Wave Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMMT.2007.381426","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 6.25 Gb/s Decision Feedback Equalizer used in SerDes for High-speed Backplane Communications
A 6.25 Gb/s two-tap DFE (decision feedback equalizer) in high-speed backplane receiver has been designed in a 0.18-mum CMOS. The pipelined architecture in the half-rate DFE achieves an increase in the transmitted data rate over conventional DFE with a small increase in area. Near end data is a 6.25 Gb/s PRBS10 with 0.5 Vp-p, and the DFE recovered data has been measured with jitter (pp) of 3 ps and a horizontal eye-opening of 0.97 UI, a vertical eye opening of 0.48 V.
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