{"title":"用于三维集成的背向硅层堆叠","authors":"C. Tan, K.N. Chen, A. Fan, R. Reif","doi":"10.1109/SOI.2005.1563545","DOIUrl":null,"url":null,"abstract":"We have successfully demonstrated a back-to-face ultra-thin silicon layer stacking based on low temperature wafer bonding and etch-back. This type of silicon layer stacking can be expanded to wafers with device and interconnect layers to fabricate three-dimensional integrated circuits (3D ICs). Electrical connection between layers can be achieved by interlayer vertical via formed by bonded Cu layers.","PeriodicalId":116606,"journal":{"name":"2005 IEEE International SOI Conference Proceedings","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"A back-to-face silicon layer stacking for three-dimensional integration\",\"authors\":\"C. Tan, K.N. Chen, A. Fan, R. Reif\",\"doi\":\"10.1109/SOI.2005.1563545\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We have successfully demonstrated a back-to-face ultra-thin silicon layer stacking based on low temperature wafer bonding and etch-back. This type of silicon layer stacking can be expanded to wafers with device and interconnect layers to fabricate three-dimensional integrated circuits (3D ICs). Electrical connection between layers can be achieved by interlayer vertical via formed by bonded Cu layers.\",\"PeriodicalId\":116606,\"journal\":{\"name\":\"2005 IEEE International SOI Conference Proceedings\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-12-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 IEEE International SOI Conference Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOI.2005.1563545\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 IEEE International SOI Conference Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOI.2005.1563545","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A back-to-face silicon layer stacking for three-dimensional integration
We have successfully demonstrated a back-to-face ultra-thin silicon layer stacking based on low temperature wafer bonding and etch-back. This type of silicon layer stacking can be expanded to wafers with device and interconnect layers to fabricate three-dimensional integrated circuits (3D ICs). Electrical connection between layers can be achieved by interlayer vertical via formed by bonded Cu layers.
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