用于σ - δ数据转换器的高保真抽取滤波器的结构设计仿真和硅实现

Conference Proceedings. 10th Anniversary. IMTC/94. Advanced Technologies in I & M. 1994 IEEE Instrumentation and Measurement Technolgy Conference (Cat. No.94CH3424-9) Pub Date : 1994-05-10 DOI:10.1109/IMTC.1994.351969

I. Kale, R. Morling, A. Krukowski, D. A. Devine

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引用次数: 5

摘要

本文报告了在直流至约16 kHz频率范围内具有24位精度的双路多相抽取滤波器的算法设计和仿真结果。该滤波器适用于非常高精度的数据转换应用，并且设计用于运行在4096 kHz的四阶/spl sigmaaspl Delta/调制器。本文还报道了该系统的定点结构设计、比较位级仿真和芯片实现

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Architectural design simulation and silicon implementation of a very high fidelity decimation filter for sigma-delta data converters

This paper reports on results from the algorithmic design and simulation of a two-path poly-phase decimation filter with 24-bit accuracy over the frequency range from dc to approximately 16 kHz. The filter is suited for very high precision data conversion applications, and has been designed for use with a fourth-order /spl Sigmaspl Delta/ modulator running at 4096 kHz. This paper also reports on the fixed-point architectural design, comparative bit-level simulations and silicon implementation.<>

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Conference Proceedings. 10th Anniversary. IMTC/94. Advanced Technologies in I & M. 1994 IEEE Instrumentation and Measurement Technolgy Conference (Cat. No.94CH3424-9)

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