Sub-micron InGaAs Esaki diodes with record high peak current density

Tunneling field effect transistors (TFET), which are gated Esaki tunnel junctions (ETD) operating in the Zener regime, have theoretically been predicted to operate with ultra low power supplies (<0.5 V) and steep subthreshold slopes (<60 mV/dec) [1, 2]. However, the majority of these projections have been made based on uncalibrated TCAD modeling. To this end, the authors experimentally demonstrate a pair of InGaAs tunnel diodes with the highest peak current densities (JP = IP/Area) ever reported for tunnel diodes (975 kA/cm2 or 9.75 mA/µm2) [3–5]. Other groups have attempted to experimentally demonstrate these structures, but were limited by a combination of output current and series resistance [6]. The key innovation in this study was a process for testing deep submicron Esaki diodes [7], which mitigates these factors.