片上静电放电(ESD)保护结构的设计与建模

2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716) Pub Date : 2004-05-16 DOI:10.1109/ICMEL.2004.1314905

J. Liou, Xiaofang Gao

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引用次数: 1

摘要

静电放电(ESD)是微芯片可靠性的关键问题。本文介绍了一种用于静电防护设计的计算机辅助设计工具及其应用。具体来说，我们开发了一个改进的、鲁棒的MOS模型，并将该模型实现到用于ESD电路仿真的行业标准Cadence SPICE中。利用传输线脉冲(TLP)技术和人体模型(HBM)测试仪测量的实验数据来支持该模型。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design and modeling of on-chip electrostatic discharge (ESD) protection structures

Electrostatic discharge (ESD) is a critical reliability concern for microchips. This paper presents a computer-aided design tool for ESD protection design and applications. Specifically, we develop an improved and robust MOS model and implement such a model into the industry standard Cadence SPICE for ESD circuit simulation. Experimental data measured from the transmission line pulsing (TLP) technique and human body model (HBM) tester are included in support of the model.

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来源期刊

2004 24th International Conference on Microelectronics (IEEE Cat. No.04TH8716)

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