A 0.8-8 GHz 9.7 mW analog-digital dual-loop adaptive-bandwidth DLL based multi-phase clock generator

This paper presents an implementation of a low-jitter wide-range multi-phase clock generator using a delay-locked loop (DLL) for ultra-wideband (UWB) application. The analog-digital dual-loop adaptive-bandwidth structure, in conjunction with a complementary phase detector (PD), ensures low-jitter clock generation over a wide frequency range. The self-feedback technique reduces the power consumption of the level-shifter circuit 50% at least. The 0.18-/spl mu/m CMOS prototype exhibits a maximum clock jitter of 3.9 ps (rms) and 28.7 ps (pk-pk) at an output clock rate of 1.6 to 8 GHz (50-250 MHz input reference frequency) and consumes 9.7 mW from a 1.8-V supply at 8 GHz.