{"title":"栅极电介质降解过程中氧空位缺陷的模型","authors":"A. Shluger, K. McKenna","doi":"10.1109/IRPS.2013.6532018","DOIUrl":null,"url":null,"abstract":"Capture and emission of carriers by point defects in gate dielectrics, such as SiO2 and HfO2, and at their interfaces with the substrate is thought to be responsible for the performance and reliability issues in MOS devices, in particular, 1/f noise, negative bias temperature instability (NBTI), and long-term dielectric reliability and degradation. The ultra-thin silicon dioxide layer present at the interface between Si and high-k films plays a critical role in the performance of high-k gate oxide stacks. However, detailed atomistic models relating device electrical characteristics to the properties of defects in gate dielectrics are only starting to emerge. We review some of the theoretical models proposed for oxygen deficient defects in silica and hafnia and their charge trapping behavior. These models are related to physical characterization of degradation processes in CMOS devices.","PeriodicalId":138206,"journal":{"name":"2013 IEEE International Reliability Physics Symposium (IRPS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"Models of oxygen vacancy defects involved in degradation of gate dielectrics\",\"authors\":\"A. Shluger, K. McKenna\",\"doi\":\"10.1109/IRPS.2013.6532018\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Capture and emission of carriers by point defects in gate dielectrics, such as SiO2 and HfO2, and at their interfaces with the substrate is thought to be responsible for the performance and reliability issues in MOS devices, in particular, 1/f noise, negative bias temperature instability (NBTI), and long-term dielectric reliability and degradation. The ultra-thin silicon dioxide layer present at the interface between Si and high-k films plays a critical role in the performance of high-k gate oxide stacks. However, detailed atomistic models relating device electrical characteristics to the properties of defects in gate dielectrics are only starting to emerge. We review some of the theoretical models proposed for oxygen deficient defects in silica and hafnia and their charge trapping behavior. These models are related to physical characterization of degradation processes in CMOS devices.\",\"PeriodicalId\":138206,\"journal\":{\"name\":\"2013 IEEE International Reliability Physics Symposium (IRPS)\",\"volume\":\"33 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-04-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE International Reliability Physics Symposium (IRPS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IRPS.2013.6532018\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE International Reliability Physics Symposium (IRPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IRPS.2013.6532018","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Models of oxygen vacancy defects involved in degradation of gate dielectrics
Capture and emission of carriers by point defects in gate dielectrics, such as SiO2 and HfO2, and at their interfaces with the substrate is thought to be responsible for the performance and reliability issues in MOS devices, in particular, 1/f noise, negative bias temperature instability (NBTI), and long-term dielectric reliability and degradation. The ultra-thin silicon dioxide layer present at the interface between Si and high-k films plays a critical role in the performance of high-k gate oxide stacks. However, detailed atomistic models relating device electrical characteristics to the properties of defects in gate dielectrics are only starting to emerge. We review some of the theoretical models proposed for oxygen deficient defects in silica and hafnia and their charge trapping behavior. These models are related to physical characterization of degradation processes in CMOS devices.