A capacitance coupled bit line cell for Mb level DRAMs

CIRCUIT TECHNIQUES developed for a stacked capacitor 256Kb NMOS DRAM test model to achieve the best use of a small cell ( 3 8 . 2 5 ~ 2 ) used as a storage element will be reported. In the development of next generation DRAMs, a certain storage capacitance value (approximately 50fF) must be assembled in the small cell area with minimal capture rate of minority carriers in the substrate. Conventional double polysilicon cells are becoming obsolete for these requirements. Among several improved cell structures, the stacked capacitor cell’ affords larger storage capacitance by extending the storage region onto the transfer gate. The use of capacitive-coupled bit lines (CCB) in triple polysilicon cell structures are similar, but have an approximately 1.5 times larger storage area, because the total cell area is utilized for the capacitor. Figure 1 shows a plane and cross sectional view of the cell. A large storage area was created by reciprocally connecting the transfer-gate and the capacitor. This has eliminated the space for a contact hole between bit line to cell. The cell output voltage of CCB and standard metal bit line structures were compared: Figure 2 shows the calculated output voltage as a function of cell size. Lateral dimensions including storage capacitors were assumed to vary with cell size, while the spacing between capacitors and the metal bit line width were kept constant because the minimum line width and the spacing were assumed. Vertical dimensions were also kept constant. A two-dimensional numerical analysis method was used for capacitance evaluation, and the effects of capacitance between adjacent bit lines were taken into account. Since the bit line width of CCB structures varies with cell size, the parasitic capacitance is comparably large for cell sizes over 4 0 m 2 and the output voltage is lower than that for metal bit line structure. But if the memory cells are very small, the situation is reversed; the capacitance of metal bit lines does not reduce much with cell size due to fringe Capacitance components and the emergence of capacitance between bit lines, while the capacitor area rapidly decreases. For the same output voltages, a CCB cell with larger storage capacitance is more resistive to soft errors and superior performance is expected from very small cells. The cell’s operational biases are slightly different from conventional cells. In write operations, bit lines are set at the V,, or Vss level according to the data being written. The voltage source lines provide a Vcc level to each storage node __