{"title":"负电容铁电器件温度效应的全耦合模拟","authors":"A. Raol, Tom Jiao, Chandana Shashidhara, H. Wong","doi":"10.1109/LAEDC51812.2021.9437945","DOIUrl":null,"url":null,"abstract":"In this paper, fully-coupled Landau–Khalatnikov (LK) and semiconductor equations are solved in a fully coupled manner to study the temperature effect on negative capacitance (NC) in ferroelectric (FE) devices. The validity of the framework is carefully verified with analytical calculations. LK parameters are calibrated to experiment. The temperature effects (100K to 500K) on the FE capacitors and FE junctionless double-gate field-effect transistor (FE-JL-DG-FET) without an internal metal gate are studied. It is found that the FE effect on negative capacitance increases at a lower temperature in both FE capacitor and FET. High dielectric constant (dielectric constant, εox = 39) oxide is required to achieve super-steep subthreshold slope (2.9mV/dec) in 300K. If regular silicon dioxide (εox = 3.9) is used, a temperature as low as 100K is required to maintain the NC effect. It is also found that at high VD, the NC effect disappears earlier than low VD.","PeriodicalId":112590,"journal":{"name":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","volume":"146 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Fully-Coupled Simulation of the Temperature Effect on Negative Capacitance Ferroelectric Devices\",\"authors\":\"A. Raol, Tom Jiao, Chandana Shashidhara, H. Wong\",\"doi\":\"10.1109/LAEDC51812.2021.9437945\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, fully-coupled Landau–Khalatnikov (LK) and semiconductor equations are solved in a fully coupled manner to study the temperature effect on negative capacitance (NC) in ferroelectric (FE) devices. The validity of the framework is carefully verified with analytical calculations. LK parameters are calibrated to experiment. The temperature effects (100K to 500K) on the FE capacitors and FE junctionless double-gate field-effect transistor (FE-JL-DG-FET) without an internal metal gate are studied. It is found that the FE effect on negative capacitance increases at a lower temperature in both FE capacitor and FET. High dielectric constant (dielectric constant, εox = 39) oxide is required to achieve super-steep subthreshold slope (2.9mV/dec) in 300K. If regular silicon dioxide (εox = 3.9) is used, a temperature as low as 100K is required to maintain the NC effect. It is also found that at high VD, the NC effect disappears earlier than low VD.\",\"PeriodicalId\":112590,\"journal\":{\"name\":\"2021 IEEE Latin America Electron Devices Conference (LAEDC)\",\"volume\":\"146 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-04-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE Latin America Electron Devices Conference (LAEDC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/LAEDC51812.2021.9437945\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE Latin America Electron Devices Conference (LAEDC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LAEDC51812.2021.9437945","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Fully-Coupled Simulation of the Temperature Effect on Negative Capacitance Ferroelectric Devices
In this paper, fully-coupled Landau–Khalatnikov (LK) and semiconductor equations are solved in a fully coupled manner to study the temperature effect on negative capacitance (NC) in ferroelectric (FE) devices. The validity of the framework is carefully verified with analytical calculations. LK parameters are calibrated to experiment. The temperature effects (100K to 500K) on the FE capacitors and FE junctionless double-gate field-effect transistor (FE-JL-DG-FET) without an internal metal gate are studied. It is found that the FE effect on negative capacitance increases at a lower temperature in both FE capacitor and FET. High dielectric constant (dielectric constant, εox = 39) oxide is required to achieve super-steep subthreshold slope (2.9mV/dec) in 300K. If regular silicon dioxide (εox = 3.9) is used, a temperature as low as 100K is required to maintain the NC effect. It is also found that at high VD, the NC effect disappears earlier than low VD.