30 nm超薄体SOI MOSFET，选择性沉积Ge提高S/D

58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526) Pub Date : 2000-06-19 DOI:10.1109/DRC.2000.877072

Yang-Kyu Choi, Yoo-Chan Jeon, P. Ranade, H. Takenuchi, T. King, J. Bokor, C. Hu

{"title":"30 nm超薄体SOI MOSFET，选择性沉积Ge提高S/D","authors":"Yang-Kyu Choi, Yoo-Chan Jeon, P. Ranade, H. Takenuchi, T. King, J. Bokor, C. Hu","doi":"10.1109/DRC.2000.877072","DOIUrl":null,"url":null,"abstract":"MOSFETs with selectively deposited Ge raised source/drain (S/D) implemented in 8 nm ultra-thin-body (UTB) SOI are demonstrated. The Ge is selectively deposited by LPCVD and annealed at a low temperature using RTA (650/spl deg/C, 20 s). Devices with gate lengths down to 30 nm are obtained with 8 nm UTB and show excellent short-channel behavior.","PeriodicalId":126654,"journal":{"name":"58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"26","resultStr":"{\"title\":\"30 nm ultra-thin-body SOI MOSFET with selectively deposited Ge raised S/D\",\"authors\":\"Yang-Kyu Choi, Yoo-Chan Jeon, P. Ranade, H. Takenuchi, T. King, J. Bokor, C. Hu\",\"doi\":\"10.1109/DRC.2000.877072\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"MOSFETs with selectively deposited Ge raised source/drain (S/D) implemented in 8 nm ultra-thin-body (UTB) SOI are demonstrated. The Ge is selectively deposited by LPCVD and annealed at a low temperature using RTA (650/spl deg/C, 20 s). Devices with gate lengths down to 30 nm are obtained with 8 nm UTB and show excellent short-channel behavior.\",\"PeriodicalId\":126654,\"journal\":{\"name\":\"58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526)\",\"volume\":\"61 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-06-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"26\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DRC.2000.877072\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.2000.877072","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 26

摘要

在8nm超薄体(UTB) SOI中实现了选择性沉积Ge升高源/漏极(S/D)的mosfet。通过LPCVD选择性沉积Ge，并通过RTA低温退火(650/spl℃，20 s)，得到栅极长度小于30 nm的器件，并具有优异的短沟道性能。

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30 nm ultra-thin-body SOI MOSFET with selectively deposited Ge raised S/D

MOSFETs with selectively deposited Ge raised source/drain (S/D) implemented in 8 nm ultra-thin-body (UTB) SOI are demonstrated. The Ge is selectively deposited by LPCVD and annealed at a low temperature using RTA (650/spl deg/C, 20 s). Devices with gate lengths down to 30 nm are obtained with 8 nm UTB and show excellent short-channel behavior.

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来源期刊

58th DRC. Device Research Conference. Conference Digest (Cat. No.00TH8526)

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