Effects of LDD spacer etches on spacer widths, subsequent oxide growths and yield enhancement

The lightly-doped drain (LDD) spacer has been used extensively in conventional CMOS processing, which leads to less hot carrier degradation. For the formation of LDD spacers, a certain thickness of TEOS layer is deposited and then a blanket etch is performed using an endpoint algorithm. However, as device sizes shrink (e.g. gate length and active area), it is important that spacers should not overlap, as this will result in improper source/drain and contact openings. The effects of LDD spacer etches have been investigated for spacer width control, subsequent oxide growths and yield enhancement.