{"title":"一个可靠的和高电压兼容CMOS I/O缓冲器","authors":"Hwang-Cherng Chow, You-Gang Chen","doi":"10.1109/MWSCAS.2004.1354392","DOIUrl":null,"url":null,"abstract":"A high voltage tolerant and reliable CMOS I/O buffer without using thick-oxide devices is presented. By the floating n-well technique, the proposed design has a simpler structure and the good gate-oxide reliability is achieved. In addition, it is dc leakage free and has no redundant pad for dual powers. From the simulation results, the proposed circuit can demonstrate both speed enhancement about 20% in pull-up operation and 50% saving in area. Therefore, the proposed I/O buffer is very suitable for mixed voltage interface applications.","PeriodicalId":185817,"journal":{"name":"The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A reliable and high voltage compatible CMOS I/O buffer\",\"authors\":\"Hwang-Cherng Chow, You-Gang Chen\",\"doi\":\"10.1109/MWSCAS.2004.1354392\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A high voltage tolerant and reliable CMOS I/O buffer without using thick-oxide devices is presented. By the floating n-well technique, the proposed design has a simpler structure and the good gate-oxide reliability is achieved. In addition, it is dc leakage free and has no redundant pad for dual powers. From the simulation results, the proposed circuit can demonstrate both speed enhancement about 20% in pull-up operation and 50% saving in area. Therefore, the proposed I/O buffer is very suitable for mixed voltage interface applications.\",\"PeriodicalId\":185817,\"journal\":{\"name\":\"The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-07-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2004.1354392\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2004.1354392","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A reliable and high voltage compatible CMOS I/O buffer
A high voltage tolerant and reliable CMOS I/O buffer without using thick-oxide devices is presented. By the floating n-well technique, the proposed design has a simpler structure and the good gate-oxide reliability is achieved. In addition, it is dc leakage free and has no redundant pad for dual powers. From the simulation results, the proposed circuit can demonstrate both speed enhancement about 20% in pull-up operation and 50% saving in area. Therefore, the proposed I/O buffer is very suitable for mixed voltage interface applications.
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