{"title":"基于FPGA的高速在线最大似然定位算法的设计","authors":"Xinyi Cheng, Yong Xiao, Yonggang Wang, Deng Li","doi":"10.1109/NSSMIC.2014.7430954","DOIUrl":null,"url":null,"abstract":"We present a high speed implementation of maximum-likelihood estimator using FPGA as positioning method for monolithic scintillation crystal based PET detector. Instead of using channel distribution parameters to recalculate the fitting curves, we suggest using real possibility distribution function for channels of all possible positions, which largely reduces the requirement of computation resources (e.g. on-chip DSP). With optimization of subordinate regions of these distributions, the whole storage requirement are trimmed to no more than one-fourth as before without loss of performance compared to an off-line implementation. The simplified hardware structure makes a tight pipelined structure possible that the event processing rate can be 25M events per second with the main clock at 200M Hz.","PeriodicalId":144711,"journal":{"name":"2014 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC)","volume":"42 5-7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Design of a high speed online maximum likelihood positioning algorithm using FPGA\",\"authors\":\"Xinyi Cheng, Yong Xiao, Yonggang Wang, Deng Li\",\"doi\":\"10.1109/NSSMIC.2014.7430954\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a high speed implementation of maximum-likelihood estimator using FPGA as positioning method for monolithic scintillation crystal based PET detector. Instead of using channel distribution parameters to recalculate the fitting curves, we suggest using real possibility distribution function for channels of all possible positions, which largely reduces the requirement of computation resources (e.g. on-chip DSP). With optimization of subordinate regions of these distributions, the whole storage requirement are trimmed to no more than one-fourth as before without loss of performance compared to an off-line implementation. The simplified hardware structure makes a tight pipelined structure possible that the event processing rate can be 25M events per second with the main clock at 200M Hz.\",\"PeriodicalId\":144711,\"journal\":{\"name\":\"2014 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC)\",\"volume\":\"42 5-7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NSSMIC.2014.7430954\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NSSMIC.2014.7430954","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of a high speed online maximum likelihood positioning algorithm using FPGA
We present a high speed implementation of maximum-likelihood estimator using FPGA as positioning method for monolithic scintillation crystal based PET detector. Instead of using channel distribution parameters to recalculate the fitting curves, we suggest using real possibility distribution function for channels of all possible positions, which largely reduces the requirement of computation resources (e.g. on-chip DSP). With optimization of subordinate regions of these distributions, the whole storage requirement are trimmed to no more than one-fourth as before without loss of performance compared to an off-line implementation. The simplified hardware structure makes a tight pipelined structure possible that the event processing rate can be 25M events per second with the main clock at 200M Hz.