U. Gogineni, Jesus A. del Alamo, Christopher S. Putnam
{"title":"45纳米CMOS技术的射频功率潜力","authors":"U. Gogineni, Jesus A. del Alamo, Christopher S. Putnam","doi":"10.1109/SMIC.2010.5422960","DOIUrl":null,"url":null,"abstract":"This paper presents the first measurements of the RF power performance of 45 nm CMOS devices with varying device widths and layouts. We find that 45 nm CMOS can deliver a peak output power density of around 140 mW/mm with a peak power-added efficiency (PAE) of 70% at 1.1 V. The PAE and Pout decrease with increasing device width because of a decrease in the maximum oscillation frequency (fmax) for large width devices. The PAE also decreases with increasing frequency because of a decrease in gain as the operating frequency approaches fmax. The RF power performance of 45 nm devices is shown to be very similar to that of 65 nm devices.","PeriodicalId":404957,"journal":{"name":"2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"30","resultStr":"{\"title\":\"RF power potential of 45 nm CMOS technology\",\"authors\":\"U. Gogineni, Jesus A. del Alamo, Christopher S. Putnam\",\"doi\":\"10.1109/SMIC.2010.5422960\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the first measurements of the RF power performance of 45 nm CMOS devices with varying device widths and layouts. We find that 45 nm CMOS can deliver a peak output power density of around 140 mW/mm with a peak power-added efficiency (PAE) of 70% at 1.1 V. The PAE and Pout decrease with increasing device width because of a decrease in the maximum oscillation frequency (fmax) for large width devices. The PAE also decreases with increasing frequency because of a decrease in gain as the operating frequency approaches fmax. The RF power performance of 45 nm devices is shown to be very similar to that of 65 nm devices.\",\"PeriodicalId\":404957,\"journal\":{\"name\":\"2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)\",\"volume\":\"34 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"30\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SMIC.2010.5422960\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMIC.2010.5422960","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents the first measurements of the RF power performance of 45 nm CMOS devices with varying device widths and layouts. We find that 45 nm CMOS can deliver a peak output power density of around 140 mW/mm with a peak power-added efficiency (PAE) of 70% at 1.1 V. The PAE and Pout decrease with increasing device width because of a decrease in the maximum oscillation frequency (fmax) for large width devices. The PAE also decreases with increasing frequency because of a decrease in gain as the operating frequency approaches fmax. The RF power performance of 45 nm devices is shown to be very similar to that of 65 nm devices.