Chen-I Chung, Jyun-Sian Jhou, Ching-Hwa Cheng, Sih-Yan Li
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Functional Built-In Delay Binning and Calibration Mechanism for On-Chip at-Speed Self Test
The self wide-range (26%~76%), fine-scale (34ps) duty cycle adjustment technique with high-precision (28ps) calibration circuit are proposed for at-speed delay test and performance binning. Test chip DFT strategies are validated fully function work by instruments and HOY wireless test system.
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