Design Of High Performance Digital Divider

In this paper, the design of high performance digital divider based on ancient Indian Vedic mathematics technique is presented. A Vedic mathematics technique called the Parāvartya Yojayet ("Transpose and Apply") is applied to obtain the high performance by reducing the propagation delay, area consumption with minimum electric power consumption. The operation of the digital divider division and other performance parameters like propagation delay and electric power consumption were calculated through Xilinx ISE 14.4 Spartan-6 FPGA with 45 nm low-power copper process technology that delivers the best balance of performance, cost, & power. The delay of the obtained 8 ÷4 bit and 16 ÷ 8 bit digital divider was only ~ 4.91 ns (with 0.08 ns slack) & ~ 5.851ns (with 0.02 ns slack), consumed ~1.3586 mW & ~1.73 mW electric power for a LUT utilization of 0.63% & 5% respectively. Computation using Vedic mathematics decreases considerable extent of iterations resulted in minimized delay and power compared to the mostly used non – Vedic (e.g. digit-recurrence, Newton–Raphson, Goldschmidt) & Vedic architectures.