在TMS320C6X DSP架构上实现MPEG-2视频解码

Conference Record of Thirty-Second Asilomar Conference on Signals, Systems and Computers (Cat. No.98CH36284) Pub Date : 1998-11-01 DOI:10.1109/ACSSC.1998.751622

S. Sriram, C. Hung

{"title":"在TMS320C6X DSP架构上实现MPEG-2视频解码","authors":"S. Sriram, C. Hung","doi":"10.1109/ACSSC.1998.751622","DOIUrl":null,"url":null,"abstract":"This paper explores implementation of MPEG-2 decoding functions (bitstream parsing, IDCT: variable length decoding, motion compensation, dequantization) in software on the TI TMS320C6X architecture. We discuss cycle count estimates for these functions; our estimates are based on optimized, functionally accurate implementations in some cases, and on analysis of C implementations of the function in other cases. We describe how we arrive at these estimates in detail, and discuss how we were able to use automatic compilation effectively for certain functions. We also compare the C6x implementation to other MPEG-2 implementations that have been reported for general purpose CPUs that support a multimedia enhanced instruction set, such as Intel Pentium (MMX), SUN UltraSPARC (VIS), and HP PA (MAX).","PeriodicalId":393743,"journal":{"name":"Conference Record of Thirty-Second Asilomar Conference on Signals, Systems and Computers (Cat. No.98CH36284)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"21","resultStr":"{\"title\":\"MPEG-2 video decoding on the TMS320C6X DSP architecture\",\"authors\":\"S. Sriram, C. Hung\",\"doi\":\"10.1109/ACSSC.1998.751622\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper explores implementation of MPEG-2 decoding functions (bitstream parsing, IDCT: variable length decoding, motion compensation, dequantization) in software on the TI TMS320C6X architecture. We discuss cycle count estimates for these functions; our estimates are based on optimized, functionally accurate implementations in some cases, and on analysis of C implementations of the function in other cases. We describe how we arrive at these estimates in detail, and discuss how we were able to use automatic compilation effectively for certain functions. We also compare the C6x implementation to other MPEG-2 implementations that have been reported for general purpose CPUs that support a multimedia enhanced instruction set, such as Intel Pentium (MMX), SUN UltraSPARC (VIS), and HP PA (MAX).\",\"PeriodicalId\":393743,\"journal\":{\"name\":\"Conference Record of Thirty-Second Asilomar Conference on Signals, Systems and Computers (Cat. No.98CH36284)\",\"volume\":\"86 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"21\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Conference Record of Thirty-Second Asilomar Conference on Signals, Systems and Computers (Cat. No.98CH36284)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ACSSC.1998.751622\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Conference Record of Thirty-Second Asilomar Conference on Signals, Systems and Computers (Cat. No.98CH36284)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ACSSC.1998.751622","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 21

摘要

本文探讨了MPEG-2解码功能(比特流解析、IDCT:变长解码、运动补偿、去量化)在TI TMS320C6X架构上的软件实现。我们讨论了这些函数的循环计数估计;在某些情况下，我们的估计是基于优化的、功能准确的实现，而在其他情况下，则是基于对该功能的C实现的分析。我们详细描述了我们是如何得出这些估计的，并讨论了我们如何能够对某些功能有效地使用自动编译。我们还将C6x实现与其他MPEG-2实现进行了比较，这些实现已被报道用于支持多媒体增强指令集的通用cpu，如Intel Pentium (MMX)、SUN UltraSPARC (VIS)和HP PA (MAX)。

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MPEG-2 video decoding on the TMS320C6X DSP architecture

This paper explores implementation of MPEG-2 decoding functions (bitstream parsing, IDCT: variable length decoding, motion compensation, dequantization) in software on the TI TMS320C6X architecture. We discuss cycle count estimates for these functions; our estimates are based on optimized, functionally accurate implementations in some cases, and on analysis of C implementations of the function in other cases. We describe how we arrive at these estimates in detail, and discuss how we were able to use automatic compilation effectively for certain functions. We also compare the C6x implementation to other MPEG-2 implementations that have been reported for general purpose CPUs that support a multimedia enhanced instruction set, such as Intel Pentium (MMX), SUN UltraSPARC (VIS), and HP PA (MAX).

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Conference Record of Thirty-Second Asilomar Conference on Signals, Systems and Computers (Cat. No.98CH36284)

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