基于细粒度多核系统的高性能并行CAVLC编码器

Zhibin Xiao, B. Baas
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引用次数: 23

摘要

提出了一种在细粒度多核系统上实现的高性能并行上下文自适应长度编码(CAVLC)编码器。软件编码器是为H.264/AVC基线配置文件编码器而设计的。利用算术表消除和压缩技术,对CAVLC编码器的数据流进行了分区,并映射到15个小处理器阵列上。对每个处理器的并行工作负载进行表征和平衡,以进一步优化吞吐量。所提出的并行CAVLC编码器实现了720p高清电视每秒30帧的实时处理要求。实验表明,该编码器的吞吐量是目前通用处理器上相同编码器的4.86 ~ 6.83倍,而且所需的芯片面积要小得多。与在普通DSP处理器上发布的实现相比,该设计具有大约1.0至6.15倍的高吞吐量,而所需的面积不到6倍。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A high-performance parallel CAVLC encoder on a fine-grained many-core system
This paper presents a high-performance parallel context-based adaptive length coding (CAVLC) encoder implemented on a fine-grained many-core system. The software encoder is designed for a H.264/AVC baseline profile encoder. By utilizing arithmetic table elimination and compression techniques, the data-flow of the CAVLC encoder has been partitioned and mapped to an array of 15 small processors. The parallel workload of each processor is characterized and balanced for further throughput optimization. The proposed parallel CAVLC encoder achieves the real-time processing requirement of 30 frames per second for 720 p HDTV. Our experiments show that the presented CAVLC encoder has 4.86 to 6.83 times higher throughput and requires far smaller chip area than the identical encoder implemented on state-of-art general-purpose processors. In comparison to published implementations on common DSP processors, the design has approximately 1.0 to 6.15 times higher throughput while requiring less than 6 times smaller area.
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