Usage and impact of multi-bit flip-flops low power methodology on physical implementation

Multi-Bit flip-flops (MBFF) usage is an innovative technique introduced in Integrated Circuit (IC) design as one of the low power methodologies that reduce the area and the power consumption during the design phase and physical synthesis. Recently this approach is introduced in the physical implementation to help for more power reduction. In this paper, we will present the MBFF merging challenges in the physical design process, then we will recommend the optimal stage to perform the flip-flops merging, within the Pre-CTS (Clock-tree Synthesis) step. The success criteria is to achieve the highest MBFF percentage without degrading the circuit performance. The experiments on a high-speed design, made with 7nm technology node, shows that the best stage for the MBFF merging is after the final detailed placement and timing optimization. The percentage of multi-bit flip-flop cells compared to all flip-flop cells achieved is 75.8% with a no performance degradation.