DLX RISC处理器的合成与物理设计

Proceedings of the Sixteenth National Radio Science Conference. NRSC'99 (IEEE Cat. No.99EX249) Pub Date : 1999-02-23 DOI:10.1109/NRSC.1999.760910

I.H. Al-Mohandes, A. Rashed, H. Ragaie, M. Elsaid

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引用次数: 2

摘要

针对32位DLX RISC处理器(称为DLXS)的非流水线版本，开发了用于AutoLogic II的VHDL可合成模型。使用Mentor Graphics EDA工具对VHDL RTL模型进行了综合、优化、仿真和布局。设计的ASIC基于CMOSN标准单元库，采用0.8 /spl mu/m技术。处理器时钟频率为33mhz，芯片面积为8.7/spl倍/9.2 mm/sup 2/。

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Synthesis and physical design of DLX RISC processor

A VHDL synthesizable model for AutoLogic II is developed for an unpipelined version of the 32-bit DLX RISC processor, called DLXS. The VHDL RTL model is synthesized, optimized, simulated, and laid out using Mentor Graphics EDA tools. The designed ASIC is based on the CMOSN standard cell library with 0.8 /spl mu/m technology. The processor clock frequency is 33 MHz and the chip area is 8.7/spl times/9.2 mm/sup 2/.

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Proceedings of the Sixteenth National Radio Science Conference. NRSC'99 (IEEE Cat. No.99EX249)

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