G. Adema, C. Berry, N. Koopman, G. Rinne, E. Yung, I. Turlik
{"title":"倒装芯片技术:一种提供高密度互连的已知优良芯片的方法","authors":"G. Adema, C. Berry, N. Koopman, G. Rinne, E. Yung, I. Turlik","doi":"10.1109/ICMCM.1994.753527","DOIUrl":null,"url":null,"abstract":"Flip chip interconnections provide the highest interconnection density possible which makes this technology very attractive for use with multichip modules. However, several factors have hindered the use of this technology. These factors include the availability of bumped wafers and the inability to test and bum-in bumped chips before they are assembled onto a multichip module. MCNC has addressed both of these concerns by establishing a wafer bumping facility and by developing a method for the test and burn-in of bare die. The solder bump formation is based upon an electroplating process. The test and burn-in of bumped chips is accomplished using a unique process which utilizes a temporary metallurgical attachment to a test substrate. These processes are described in detail in the following sections.","PeriodicalId":363745,"journal":{"name":"Proceedings of the International Conference on Multichip Modules","volume":"118 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"Flip Chip Technology: A Method for Providing Known Good Die with High Density Interconnections\",\"authors\":\"G. Adema, C. Berry, N. Koopman, G. Rinne, E. Yung, I. Turlik\",\"doi\":\"10.1109/ICMCM.1994.753527\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Flip chip interconnections provide the highest interconnection density possible which makes this technology very attractive for use with multichip modules. However, several factors have hindered the use of this technology. These factors include the availability of bumped wafers and the inability to test and bum-in bumped chips before they are assembled onto a multichip module. MCNC has addressed both of these concerns by establishing a wafer bumping facility and by developing a method for the test and burn-in of bare die. The solder bump formation is based upon an electroplating process. The test and burn-in of bumped chips is accomplished using a unique process which utilizes a temporary metallurgical attachment to a test substrate. These processes are described in detail in the following sections.\",\"PeriodicalId\":363745,\"journal\":{\"name\":\"Proceedings of the International Conference on Multichip Modules\",\"volume\":\"118 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-04-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the International Conference on Multichip Modules\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICMCM.1994.753527\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the International Conference on Multichip Modules","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMCM.1994.753527","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Flip Chip Technology: A Method for Providing Known Good Die with High Density Interconnections
Flip chip interconnections provide the highest interconnection density possible which makes this technology very attractive for use with multichip modules. However, several factors have hindered the use of this technology. These factors include the availability of bumped wafers and the inability to test and bum-in bumped chips before they are assembled onto a multichip module. MCNC has addressed both of these concerns by establishing a wafer bumping facility and by developing a method for the test and burn-in of bare die. The solder bump formation is based upon an electroplating process. The test and burn-in of bumped chips is accomplished using a unique process which utilizes a temporary metallurgical attachment to a test substrate. These processes are described in detail in the following sections.