循环诱导的65nm FPGA闪存开关退化

2010 IEEE International Integrated Reliability Workshop Final Report Pub Date : 2010-10-01 DOI:10.1109/IIRW.2010.5706495

Ben A. Schmid, J. Jia, J. Wolfman, Yu Wang, F. Dhaoui, Huan-Chung Tseng, Sung-Rae Kim, Kin-Sing Lee, Patty Liu, K. Han, C. Hu

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引用次数: 3

摘要

我们提出了一个研究循环诱导退化的双晶体管闪存单元与一个共享浮栅。该单元直接用作65纳米嵌入式闪存工艺制造的现场可编程门阵列(FPGA)中的可配置互连开关。通过优化多再氧化、LDD植入和间隔模块，电池续航能力在单电池和1mbit测试阵列水平上都得到了显著提高。

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Cycling induced degradation of a 65nm FPGA flash memory switch

We present a study of cycling induced degradation of a two transistor Flash memory cell with a shared floating gate. The cell directly serves as a configurable interconnection switch in a Field Programmable Gate Array (FPGA) fabricated with a 65 nm embedded-Flash process. By optimizing the poly re-oxidation, LDD implant and spacer module, the cell endurance is significantly improved at both the single cell and 1 Mbit test-array levels.

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来源期刊

2010 IEEE International Integrated Reliability Workshop Final Report

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